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    Untitled

    Abstract: No abstract text available
    Text: SM372SDSFN3XGXX December 1995 Rev 0 SMART Modular Technologies SM372SDSFN3XGXX 512KByte 64Kx72 Synchronous Secondary Cache SRAM Module General Description Features The SM372SDSFN3XGXX is a high performance, 512 Kilobyte synchronous secondary cache SRAM module. It


    Original     		PDF SM372SDSFN3XGXX 512KByte 64Kx72) SM372SDSFN3XGXX 168-pin, 32Kx36

    723653

    Abstract: 72V7290 72V3613 72V7250 72V3611 72V3623 72V72100 72V7230 72V7240 72V7260
    Text: Selector Guide for FIFO Memory Products • Synchronous FIFOs SuperSync II, SuperSync™ SyncFIFO™, DualSync™ • Bi-Directional Synchronous FIFOs • Asynchronous FIFOs the leading provider of FIFO memories. July’00 IDT FIFO Memory Products Quick Reference Guide


    Original     		PDF 512-bit 16K-bit 64K-bit 128K-bit 256K-bit 512K-bit 100MHz 133MHz 723653 72V7290 72V3613 72V7250 72V3611 72V3623 72V72100 72V7230 72V7240 72V7260

    723653

    Abstract: BI 7284 72V7250 72V72100 72V7230 72V7240 72V7260 72V7270 72V7280 72V7290
    Text: Selector Guide for FIFO Memory Products • Synchronous FIFOs SuperSync II, SuperSync™ SyncFIFO™, DualSync™ • Bi-Directional Synchronous FIFOs • Asynchronous FIFOs the leading provider of FIFO memories. Jan’00 IDT FIFO Memory Products Quick Reference Guide


    Original     		PDF 512-bit 16K-bit 64K-bit 128K-bit 512K-bit 7236x3/72V36x3 723653 BI 7284 72V7250 72V72100 72V7230 72V7240 72V7260 72V7270 72V7280 72V7290

    75P52100

    Abstract: AN-278 IDT75P52100 AN278
    Text: IDT75P52100: Basic Table Maintenance Operation Application Brief AN-278 To request the full AN-278 application note, please contact your local IDT Sales Representative at 1-800-754-4555 Overview Background The application note "IDT75P52100: Basic Table Maintenance


    Original     		PDF IDT75P52100: AN-278 AN-278 IDT75P52100 DSC-5341/00 75P52100 AN278

    BE5L

    Abstract: CYD18S18V18 CYD09S36V18 CYD18S36V18 SKR 175 FullFlex36
    Text: FullFlex FullFlex Synchronous SDR Dual Port SRAM Features Functional Description • True dual port memory enables simultaneous access to the shared array from each port ■ Synchronous pipelined operation with Single Data Rate SDR operation on each port


    Original     		PDF

    FullFlex36

    Abstract: No abstract text available
    Text: FullFlex FullFlex Synchronous DDR Dual-Port SRAM Features • True dual-ported memory allows simultaneous access to the shared array from each port • Synchronous pipelined operation with selectable Double Data Rate DDR or Single Data Rate (SDR) operation on each port


    Original     		PDF 36-Gb/s 484-ball 256-ball FullFlex72 CYDD36S72V18) CYDD18S72V1t 27mmx27mmx2 36Mx36 36Mx18 FullFlex36

    FullFlex36

    Abstract: No abstract text available
    Text: PRELIMINARY FullFlex Synchronous DDR Dual-Port SRAM Features • True dual-ported memory allows simultaneous access to the shared array from each port • Synchronous pipelined operation with selectable Double Data Rate DDR or Single Data Rate (SDR) operation on each port


    Original     		PDF 36-Gb/s 484-ball 256-ball FullFlex72 CYDD36S72V18) CYDD18S72V18 XS36V18 CYDXXS18V18 BW256 FullFlex36

    FullFlex36

    Abstract: No abstract text available
    Text: FullFlex FullFlex Synchronous DDR Dual-Port SRAM Features • True dual-ported memory allows simultaneous access to the shared array from each port • Synchronous pipelined operation with selectable Double Data Rate DDR or Single Data Rate (SDR) operation on each port


    Original     		PDF 36-Gb/s 484-ball 256-ball FullFlex72 CYDD36S72V18) CYDD18S72V1mation 27mmx27mmx2 36Mx36 36Mx18 FullFlex36

    75P42100

    Abstract: 75P52100 AN-280 IPCS
    Text: Implementing 36-bit Lookups Using 75P52100/75P42100 IPCs Application Brief AN-280 To request the full application note, please contact your local IDT Sales Representative or call 1-831-754-4555 Overview Application Note Topics This application note “Implementing 36-bit Lookups using IDT's


    Original     		PDF 36-bit 75P52100/75P42100 AN-280 36-bit 72-bit, 144bit, 288-bit 576-bit 75P42100 75P52100 AN-280 IPCS

    75P42100

    Abstract: 75P52100 AN-277 idt cam
    Text: IDT 75P42100/75P52100 Power Management Application Brief AN-277 To request the full application note, please contact your local IDT Sales Representative or call 1-800-754-4555 Overview Background IDT's 75P42100 and 75P52100 IPCs provide power management features and the application note “IDT 75P42100/75P52100 Power


    Original     		PDF 75P42100/75P52100 AN-277 75P42100 75P52100 75P42100/75P52100 comm76 DSC-5339/01 AN-277 idt cam

    Untitled

    Abstract: No abstract text available
    Text: 67 CYM9265/CYM9266 CYM9267/CYM9268 PRELIMINARY 64K/128K/256K/512K x 72 SRAM Modules Features • Operates at 133 MHz • Uses 128K x 18, or 256K x 18 high performance synchronous SRAMs • 168-position Angled DIMM from Amp p/n 179508-2 • 3.3V inputs/data outputs


    Original     		PDF CYM9265/CYM9266 CYM9267/CYM9268 64K/128K/256K/512K 168-position CYM9265, CYM9266, CYM9267, CYM9268

    emcp 162

    Abstract: DL10 DL12 emcp TEA 2111 WT111 eMCP qualification dh29 code
    Text: WC64P603EV-XQ3X RISC 603e MODULE, SECONDARY L2 CACHE ADVANCED * MAIN FEATURES • Based on RISC 603e 3.3V Microprocessor ■ Processor Clock Frequencies: 66.6, 80, 100 MHz ■ Footprint compatible with 603e µp CQFP package ■ Bus Clock Frequencies: Up to 66.6 MHz


    Original     		PDF WC64P603EV-XQ3X 32-bit Bus/64-bit 16KByte 512KByte 64Kx72) Packaging240 P603E 240-Pin emcp 162 DL10 DL12 emcp TEA 2111 WT111 eMCP qualification dh29 code

    Untitled

    Abstract: No abstract text available
    Text: CYM9265/CYM9266 CYM9267/CYM9268 PRELIMINARY 64K/128K/256K/512K x 72 SRAM Modules Features • Operates at 133 MHz • Uses 128K x 18, or 256K x 18 high performance synchronous SRAMs • 168-position Angled DIMM from Amp p/n 179508-2 • 3.3V inputs/data outputs


    Original     		PDF CYM9265/CYM9266 CYM9267/CYM9268 64K/128K/256K/512K 168-position CYM9265, CYM9266, CYM9267, CYM9268

    CYD18S18V18

    Abstract: FullFlex36 CYD09S36V18 CYD18S36V18 ARRAY VCSEL
    Text: PRELIMINARY FullFlex Synchronous SDR Dual-Port SRAM Features • True dual-ported memory allows simultaneous access to the shared array from each port • Synchronous pipelined operation with SDR operation on each port — Single Data Rate SDR interface at 250 MHz


    Original     		PDF 36-Gb/s 484-ball 256-ball FullFlex72 36-Mbit: CYD36S72V18) FullFlex36 FullFlex18 CYD18S18V18 CYD09S36V18 CYD18S36V18 ARRAY VCSEL

    TMS 1070 NL

    Abstract: BE5L NA820 str 350-430 FullFlex36 CYD04S18V18 CYD36S18V18-133BGI CYD36S36V18-133BGI CYD36S72V18-133BGI tca 780
    Text: FullFlex FullFlex Synchronous SDR Dual-Port SRAM Features • True dual-ported memory allows simultaneous access to the shared array from each port • Synchronous pipelined operation with Single Data Rate SDR operation on each port — SDR interface at 250 MHz


    Original     		PDF 36-Gb/s 484-ball 256-ball FullFlex72 36-Mbit: CYD36S72V18) 36Mx72 TMS 1070 NL BE5L NA820 str 350-430 FullFlex36 CYD04S18V18 CYD36S18V18-133BGI CYD36S36V18-133BGI CYD36S72V18-133BGI tca 780

    BGA 144

    Abstract: 208 BGA 72T3665 240-BGA 72T36125
    Text: Selector Guide for TeraSync FIFOs from the leading provider of FIFO solutions • 2.5V core voltage • 225 MHz high-speed operation • Densities up to 9 M-bit • 9, 18, 36, 72-bit configurations • BGA packaging, including JTAG TeraSync the next generation


    Original     		PDF 72-bit 16Kx72 32Kx72 64Kx72 128Kx72 72T7285 72T7295 72T72105 72T72115 72T3645 BGA 144 208 BGA 72T3665 240-BGA 72T36125

    FullFlex36

    Abstract: 2BE6
    Text: FullFlex FullFlex Synchronous DDR Dual-Port SRAM Features • True dual-ported memory allows simultaneous access to the shared array from each port • Synchronous pipelined operation with selectable Double Data Rate DDR or Single Data Rate (SDR) operation on each port


    Original     		PDF 36-Gb/s 6Mx18 36Mx72 CYDD36S72V18 FullFlex36 2BE6

    DQ12-DQ15

    Abstract: CYDXXS36V18 16-SD FullFlex36
    Text: PRELIMINARY FullFlex Synchronous DDR Dual-Port SRAM Features • True dual-ported memory allows simultaneous access to the shared array from each port • Synchronous pipelined operation with selectable Double Data Rate DDR or Single Data Rate (SDR) operation on each port


    Original     		PDF 18-Mbit, 36-Mbit CYDXXS36V18 CYDXXS18V18 256-Ball BW256 FullFlex36 484-ball FullFlex18 DQ12-DQ15 16-SD

    9261A

    Abstract: CYM9260 CYM9263 PM44 9261
    Text: fax id: 2042 3g~ yr pyprfs^ PRELIMINARY CYM9260 CYM9261A/B CYM9262A/B CYM9263 64K x 72 SRAM 128K x 72 SRAM 256K x 72 SRAM 512K x 72 SRAM Features Module Module Module Module 9262B, 9263 SRAM’s in plastic surface mount packages on an epoxy laminate board with pins. The modules are designed


    OCR Scan     		PDF CYM9260 CYM9261A/B CYM9262A/B CYM9263 18/128K 168-position CYM9260, CYM9261, CYM9262 CYM9263 9261A PM44 9261

    TLBI

    Abstract: No abstract text available
    Text: C 3 WC64P603EV-XQ3X WHITE /MICROELECTRONICS RISC 603e M ODULE, SECONDARY L2 CACHE ADVANCED * MAI N FEATURES • Based on R IS C 6 0 3 e 3 .3 V M icro p ro cessor ■ Footprint com patible w ith 603e [jp C Q FP package ■ ■ Processor C lo ck Frequencies: 66.6, 8 0 ,1 0 0 M Hz


    OCR Scan     		PDF WC64P603EV-XQ3X 32-bit Bus/64-bit 16KByte 240-Pin 80MHz 100MHz TLBI

    9261A

    Abstract: No abstract text available
    Text: fax id: 2042 3g~ yr pyprfs^ PRELIMINARY CYM9260 CYM9261A/B CYM9262A/B CYM9263 64K x 72 SRAM 128K x 72 SRAM 256K x 72 SRAM 512K x 72 SRAM Features • Operates at 50 MHz. • Uses 64K x 1 8 /1 28K x 18 or 256K x 18 high perform ance synchronous SRAMs. • 168-position Angled DIMM from Amp p/n 179508-2


    OCR Scan     		PDF CYM9260 CYM9261A/B CYM9262A/B CYM9263 168-position CYM9260, CYM9262 CYM9263 9262B, 9261A

    circuit diagram with IC 7476

    Abstract: 600/DG34-1021-36-1012-F
    Text: ADVANCE I^ IC R D N 32K, 64K SYNCHRONOUS SRAM MODULE X MT2LSYT3272B2, MT4LSYT6472B2 72 SYNCHRONOUS SRAM MODULE 32K, 64K x 72 SRAM +3.3V SUPPLY WITH CLOCKED, REGISTERED INPUTS AND BURST COUNTER FEATURES PIN ASSIGNMENT Top View 160-Lead, Dual Read-out DIMM


    OCR Scan     		PDF MT2LSYT3272B2, MT4LSYT6472B2 200ms 001Db53 circuit diagram with IC 7476 600/DG34-1021-36-1012-F

    TC 9260 P

    Abstract: 64k X 8 30-pin SIMM
    Text: CYM9260 CYM9261B CYM9262A CYM9263 64K x72SR A M 128Kx 72 SRAM 256K x 72 SRAM 512K x 72 SRAM Features • Operates at 66 MHz • Uses 64K x 1 8 ,128K x 18, or 256K x 18 high perfor­ mance synchronous SRAMs • 168-position Angled DIMM from Amp p/n 179508-2


    OCR Scan     		PDF CYM9260 CYM9261B CYM9262A CYM9263 x72SR 128Kx 168-position CYM9260, CYM9262, CYM9263 TC 9260 P 64k X 8 30-pin SIMM

    AFB3

    Abstract: No abstract text available
    Text: VZÄ WC64P603EV-XQ3X WHITE /MICROELECTRONICS RISC603e MODULE, SECONDARY L2 CACH E ADVANCED * MAI N FEATURES Based on RISC 603e 3.3V M icroprocessor • Footprint c o m p a tib le w ith 603e jup CQFP package ■ Processor C lock Frequencies: 66.6, 8 0 ,1 0 0 M H z


    OCR Scan     		PDF WC64P603EV-XQ3X RISC603e 16KByte 240-Pin AFB3