3D7005
Abstract: 3D7005-25 3D7005-30 3D7005-35 74LS SOIC300mil
Text: DATA DELAY DEVICES INC b 3E D 5b443fl2 O Q D t n A b 354 DDD All Silicon Delay Line SERIES: 3D7005 5 Taps DESCRIPTION PIN DESCRIPTION The 3D7000* series delay line is a completely silicon delay line, which features unique circuits to compensate for temperature and power supply variations. It offers 5
|
OCR Scan
|
PDF
|
2b443flE
3D7005
3D7000*
74F04
3D7005-25
3D7005-30
3D7005-35
74LS
SOIC300mil
|
DPG-41
Abstract: No abstract text available
Text: zFast L o g ic data delay devices; me. Delayed Pulse Generator SERIES: T2L Interfaced 8 pin DIP DPG-41 Features: • ■ ■ ■ Low Cost. Completely interfaced for TTL. Low profile. Fits standard 8 pins DIP socket. Specifications: ■ ■ ■ ■ ■ ■
|
OCR Scan
|
PDF
|
DPG-41
DPG-41
-10-25M
DPG-41-(
|
Untitled
Abstract: No abstract text available
Text: 3D7304 data \Q^S> delay devices^i«. MONOLITHIC QUADRUPLE FIXED DELAY LINE SERIES 3D7304 PACKAGES FEATURES • All-silicon, low-power CMOS technology 11 c 1 ^ 1 4 □ VDD TTL/CMOS compatible inputs and outputs N/C c 2 13 □ N/C Vapor phase, IR and wave solderable
|
OCR Scan
|
PDF
|
3D7304
3D7304)
500ns
0C-70C)
3D7304G
14-pin
10Kii
2b443flE
|
Untitled
Abstract: No abstract text available
Text: 2bMM3fl2 O D O l l b b 17b Multiple Monolithic Programmable Delay Lines SERIES: MPDU 8 BITS Parallel S e r ia l IN, C 1 AE, £ IN, Features 16 3 2 L 3 C 4 AE? Q 5 • ■ ■ ■ ■ ■ ■ All-silicon delay line technology Multiple PDU’s (2 ,4 ,8 ) per package
|
OCR Scan
|
PDF
|
281or
281Sor
481or
481Sor
|