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    74AS113

    Abstract: S113
    Text: PRELIMINARY Semiconductor 54AS113/DM74AS113 Dual J-K Negative-EdgeTriggered Flip-Flops with Preset General Description Features The 54AS113 is a dual-edge-triggered flip -flo p s . Each flip -flo p has individual J, K, clock, and preset inputs, and also com plem entary Q and Q ou tputs.


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    PDF DM54AS113/DM74AS113 DM54AS113 DM54AS113 DM74AS113 TL/F/6286-2 74AS113 S113