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    54LS112 Search Results

    54LS112 Result Highlights (4)

    Part ECAD Model Manufacturer Description Download Buy
    SNJ54LS112AJ Texas Instruments Dual J-K Negative-Edge-Triggered Flip-Flops With Preset And Clear 16-CDIP -55 to 125 Visit Texas Instruments Buy
    SNJ54LS112AW Texas Instruments Dual J-K Negative-Edge-Triggered Flip-Flops With Preset And Clear 16-CFP -55 to 125 Visit Texas Instruments Buy
    SNJ54LS112AFK Texas Instruments Dual J-K Negative-Edge-Triggered Flip-Flops With Preset And Clear 20-LCCC -55 to 125 Visit Texas Instruments Buy
    SN54LS112AJ Texas Instruments Dual J-K Negative-Edge-Triggered Flip-Flops With Preset And Clear 16-CDIP -55 to 125 Visit Texas Instruments
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    54LS112 Price and Stock

    Rochester Electronics LLC 54LS112FM

    J-K FLIP-FLOP
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    DigiKey 54LS112FM Bulk 202
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    Rochester Electronics LLC SN54LS112AJ

    J-K FLIP-FLOP
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    DigiKey SN54LS112AJ Bulk 30
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    Fairchild Semiconductor Corporation DM54LS112DM

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    Bristol Electronics DM54LS112DM 188
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    Texas Instruments SNC54LS112AJ

    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Bristol Electronics SNC54LS112AJ 127
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    National Semiconductor Corporation DM54LS112J/883

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    Bristol Electronics DM54LS112J/883 107
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    Find more 54LS112 price and stock on Findchips.com

    54LS112 Datasheets (21)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    54LS112 National Semiconductor Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear and Complementary OP Original PDF
    54LS112 Fairchild Semiconductor Full Line Condensed Catalogue 1977 Scan PDF
    54LS112 Raytheon Dual J-K Negative-Edge-Triggered Flip-Flops Scan PDF
    54LS112A/BEAJC Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    54LS112A/BFAJC Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    54LS112AM/B2AJC Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    54LS112DM Fairchild Semiconductor Dual JK Negative Edge Triggered Flip-Flop Scan PDF
    54LS112DM Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    54LS112DMQB Fairchild Semiconductor Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs Scan PDF
    54LS112DMQB Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    54LS112DMQB National Semiconductor DUAL NEGATIVE-EDGE-TRIGERED MASTER-SLAVE J-K FLIP-FLOPS WITH PRESET CLEAR and COMPLEMENTARY OUTPUTS Scan PDF
    54LS112DMQB National Semiconductor Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs Scan PDF
    54LS112FM Fairchild Semiconductor Dual JK Negative Edge Triggered Flip-Flop Scan PDF
    54LS112FMQB Fairchild Semiconductor Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs Scan PDF
    54LS112FMQB Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    54LS112FMQB National Semiconductor DUAL NEGATIVE-EDGE-TRIGERED MASTER-SLAVE J-K FLIP-FLOPS WITH PRESET CLEAR and COMPLEMENTARY OUTPUTS Scan PDF
    54LS112FMQB National Semiconductor Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs Scan PDF
    54LS112IMQB National Semiconductor Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs Scan PDF
    54LS112LMQB Fairchild Semiconductor Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs Scan PDF
    54LS112LMQB Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF

    54LS112 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    dm74ls112an

    Abstract: 54LS112 54LS112DMQB 54LS112FMQB 54LS112LMQB DM54LS112A DM54LS112AJ DM54LS112AW DM74LS112A DM74LS112AM
    Text: 54LS112 54LS112A DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset Clear and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs The J and


    Original     		PDF 54LS112 DM54LS112A DM74LS112A dm74ls112an 54LS112DMQB 54LS112FMQB 54LS112LMQB DM54LS112AJ DM54LS112AW DM74LS112A DM74LS112AM

    ay-5-1012

    Abstract: ali m 3329 PROCESSOR ALI 3329 ali 3329 b ali 3329 SN74188 sn74s188 str 52100 SN7452 replacement of bel 187 transistor
    Text: GENERAL INFORMATION lie of Contents • Alphanumeric Index • Selection Guides • Glossary INTERCHANGEABiliTY GUIDE MOS MEMORIES TTL MEMORIES ECl MEMORIES MICROPROCESSOR SUMMARY 38510/MACH IV PROCUREMENT SPECIFICATION JAN Mll-M-38510 INTEGRATED CIRCUITS


    Original     		PDF 38510/MACH Mll-M-38510 Z501300 Z501200 Z501201 Z012510 ZOl1510 ay-5-1012 ali m 3329 PROCESSOR ALI 3329 ali 3329 b ali 3329 SN74188 sn74s188 str 52100 SN7452 replacement of bel 187 transistor

    m38510/06301

    Abstract: M38510-06302 m38510 m38510/20702 M38510/00801 M38510/00104 m38510/01201 M38510/20802 82S62 M38510/01302
    Text: JAN/SMD Devices JAN/SMD Source JAN/SMD Source JAN/SMD Source M38510/00101 5430 M38510/07701 54S138 M38510/31512 54LS163A M38510/00102 5420 M38510/07702 54S139 M38510/31601 54LS75 M38510/00103 5410 M38510/07801 54S181 M38510/31603 54LS259 M38510/00104 5400


    Original     		PDF M38510/00101 M38510/07701 54S138 M38510/31512 54LS163A M38510/00102 M38510/07702 54S139 M38510/31601 54LS75 m38510/06301 M38510-06302 m38510 m38510/20702 M38510/00801 M38510/00104 m38510/01201 M38510/20802 82S62 M38510/01302

    Untitled

    Abstract: No abstract text available
    Text: SN 54LS112A , S N 54S 112, SN 74LS112A , S N 74S 112A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP FLOPS W ITH PRESET AND CLEAR D 2 6 6 1 . APRIL 1 9 8 2 - REVISED M A R C H 1 9 8 8 Fully Buffered to Offer Maximum Isolation from External Disturbance r a a SN 54LS 112A , SN 54S 112 . . . J OR W PACKAGE


    OCR Scan     		PDF 54LS112A 74LS112A

    dm74 Series

    Abstract: 63821 54LS112 54LS112DMQB 54LS112FMQB DM54LS112AJ DM54LS112AW DM74 DM74LS112AN LS112AM
    Text: LS112A National Semiconductor 54LS112/54LS112A/DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and


    OCR Scan     		PDF 54LS112/DM54LS112A/DM74LS112A dm74 Series 63821 54LS112 54LS112DMQB 54LS112FMQB DM54LS112AJ DM54LS112AW DM74 DM74LS112AN LS112AM

    Untitled

    Abstract: No abstract text available
    Text: LS112A National Semiconductor 54LS112/54LS112A/DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the


    OCR Scan     		PDF LS112A 54LS112/DM54LS112A/DM74LS112A

    CP12A-1

    Abstract: No abstract text available
    Text: M MOTOROLA M ilitary 54LS112A D u a l J -K Flip-Flop W ith C le a r an d Pre se t ELECTRICALLY TESTED PER: MIL-M-38510/30103 The 54LS112A dual flip-flop features individual J, K, clock, and asyn­ chronous set and clear inputs to each flip-flop. When the clock goes


    OCR Scan     		PDF MIL-M-38510/30103 54LS112A 54LS112A JM38510/30103BXA 54LS112A/BXAJC CP12A-1

    Untitled

    Abstract: No abstract text available
    Text: & > M ilitary 54LS112A MOTOROLA Dual J -K Flip-Flop W ith C lear and P reset lllllll ELECTRICALLY TESTED PER: MIL-M-38510/30103 M PO The 54LS112A dual flip-flop features individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes


    OCR Scan     		PDF 54LS112A MIL-M-38510/30103 54LS112A JM38510/30103BXA 54LS112A/BXAJC

    Untitled

    Abstract: No abstract text available
    Text: & June 1989 54LS112/54LS112A/DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-trig­ gered J-K flip-flops with complementary outputs. The J and


    OCR Scan     		PDF 54LS112/DM54LS112A/DM74LS112A

    O406

    Abstract: 54LS112 54LS112DMQB 54LS112FMQB 54LS112LMQB DM54LS112AJ DM54LS112AW DM74LS112AM DM74LS112AN E20A
    Text: June 1989 54LS112/54LS112A/DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-trig­ gered J-K flip-flops with complementary outputs. The J and


    OCR Scan     		PDF 54LS112/DM54LS112A/DM74LS112A O406 54LS112 54LS112DMQB 54LS112FMQB 54LS112LMQB DM54LS112AJ DM54LS112AW DM74LS112AM DM74LS112AN E20A

    54LS112

    Abstract: No abstract text available
    Text: M MOTOROLA M ilitary 54LS112A Dual J -K Flip-Flop W ith C lear and P reset MPO lllflll ELECTRICALLY TESTED PER: MIL-M-38510/30103 The 54LS112A dual flip-flop features individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes


    OCR Scan     		PDF MIL-M-38510/30103 54LS112A 54LS112A JM38510/30103BXA 54LS112A/BXAJC 54LS112

    74LS112AN

    Abstract: 74LS112AM
    Text: I R C H I L D S E M I C O N D U C T O R TM DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains tw o independent negative-edge-triggered J-K flip-flops w ith com plem entary


    OCR Scan     		PDF DM74LS112A DM74LS112A 74LS112AN 74LS112AM

    54LS112

    Abstract: 54LS112DMQB 54LS112FMQB 54LS112LMQB DM54LS112AJ DM54LS112AW DM74LS112A DM74LS112AM DM74LS112AN E20A
    Text: S E M IC O N D U C T O R tm DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains tw o independent negative-edge-triggered J-K flip-flops w ith com plem entary


    OCR Scan     		PDF DM74LS112A 54LS112 54LS112DMQB 54LS112FMQB 54LS112LMQB DM54LS112AJ DM54LS112AW DM74LS112A DM74LS112AM DM74LS112AN E20A

    74s188 programming

    Abstract: 74S471 N82S06 74S470 dip18 package str 52100 MARKING CODE N-CHANNEL MOS FIELD EFFECT TRANSISTOR 74S472 PROM PROGRAMMING 8080a 74S287 programming instructions
    Text: The E ngineering Staff of TEXAS INSTRUMENTS INCORPORATED Semiconductor Memory Data Book y for \ T exas In Design Engineers s t r u m e n t s >le of Contents • Alphanumeric Index • GENERAL INFORMATION Selection Guides • Glossary INTERCHANGEABILITY GUIDE


    OCR Scan     		PDF 38510/MACH MIL-M-38510 74s188 programming 74S471 N82S06 74S470 dip18 package str 52100 MARKING CODE N-CHANNEL MOS FIELD EFFECT TRANSISTOR 74S472 PROM PROGRAMMING 8080a 74S287 programming instructions

    SN74ALS123

    Abstract: SN7401 74LS424 54175 SN74298 SN74265 SN74LS630 SN74LS69 National Semiconductor Linear Data Book Transistor AF 138
    Text: INDEX • FUNCTIONAL SELECTION GUIDE • NUMERICAL FUNCTION INTERCHANGEABILITY GUIDE GENERAL INFORMATION AND EXPLANATION OF NEW LOGIC SYMBOLS ORDERING INSTRUCTIONS AND MECHANICAL DATA 54/74 SERIES OF COMPATIBLE TTL CIRCUITS • PIN OUT DIAGRAMS 54/74 FAMILY SSI CIRCUITS


    OCR Scan     		PDF MIL-M-38510 SN74ALS123 SN7401 74LS424 54175 SN74298 SN74265 SN74LS630 SN74LS69 National Semiconductor Linear Data Book Transistor AF 138

    dm8130

    Abstract: 54175 DM74367 KS 2102 7486 ic truth table signetics 2502 ci 8602 gn block diagram ci 8602 gn 74s281 DM74LS76
    Text: 19 7 6 N atio n al S e m ico n d u cto r C o rp . p 1 ? I m • ' % TTL Data Book D EV IC E MIL i 2502 2503 2504 5400 54H00 54L00 54LS00 5401 54H01 54L01 54LS01 5402 54L02 54LS02 5403 54L03 54LS03 5404 54H04 54L04 54LS04 5405 54H05 54L05 54LS05 5406 5407 5408


    OCR Scan     		PDF 54H00 54L00 54LS00 54H01 54L01 54LS01 54L02 54LS02 54L03 54LS03 dm8130 54175 DM74367 KS 2102 7486 ic truth table signetics 2502 ci 8602 gn block diagram ci 8602 gn 74s281 DM74LS76

    DM74367

    Abstract: 54175 71ls97 DM74109 DM8160 om541 ci 8602 gn block diagram 5401 DM transistor 74L10 74S136
    Text: N ational Semiconductor Section 1 - 54/74 SSI DEVICES Connection Diagram s • Electrical Tables Section 2 - 54/74 M SI DEVICES Section 3 - National Semiconductor PROPRIETARY DEVICES Section 4 - National Semiconductor ADDITIONAL D EV KES t o NATIONAL Manufactured under one or more of the fo llowing U.S. patents: 3083262, 3189758, 3231797 , 3303356, 3317671, 3323071, 3381071, 3408542, 3421025, 3426423, 3440498, 3518750, 3519897, 3557431, 3560765,


    OCR Scan     		PDF

    54LS641

    Abstract: CD Octal D-type flip-flop 74LS00 QUAD 2-INPUT NAND GATE 54LS642 54LS154 74LS00 quad TTL nand gate 74ls00 NAND gate SchottkyBarrierDiode 54LS92 54LS623
    Text: MAXIMUM RATINGS Supply Voltage - Vcc T h e S e rie s 5 4 L S /7 4 L S Schottky TTL family features both Schottky-barrier-diode inputs and em itte r inputs and u tilizes full Schottky-barrier-diode clamping to achieve speeds com parable to Series 54/74 at one-fifth of the


    OCR Scan     		PDF 54LS00 74LS00 24-LEAD 20-LEAD 54LS390/E 54LS393/C 54LS395A/E 54LS445/E 54LS490/E 54LS533/R 54LS641 CD Octal D-type flip-flop 74LS00 QUAD 2-INPUT NAND GATE 54LS642 54LS154 74LS00 quad TTL nand gate 74ls00 NAND gate SchottkyBarrierDiode 54LS92 54LS623

    54s112

    Abstract: 74LS112A 74S112
    Text: 54LS112A, SN54S112, SN74LS112A. SN74S112A DUAL J K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR _ Fully Buffered to Offer Maximum Isolation from External Disturbance • D 2 6 6 1 . A P R IL 1 9 8 2 - R E V I S E D M A R C H 1 9 8 8


    OCR Scan     		PDF SN54LS112A, SN54S112, SN74LS112A. SN74S112A 54S112, 54s112 74LS112A 74S112

    LG color tv Circuit Diagram schematics

    Abstract: texas ttl YJ 162A Texas Instruments TTL integrated circuits catalog SN74180 AC digital voltmeter using 7107 Sii 9024 MC3123 sn74ls860 SN7490AJ sn74243
    Text: IN D EXES Alphanumeric • Functional/Selection Guide IN T E R C H A N G E A B ILIT Y GUIDE G E N E R A L INFORM ATION O RD ERIN G IN STRUCTIO N S AND M ECH A N ICA L D A TA 5 4 /7 4 FA M ILIE S OF CO M PATIBLE T T L C IR C U ITS 54/74 F A M IL Y SSI C IR C U ITS


    OCR Scan     		PDF MIL-M-38510 38510/MACH 3186J Z501201 Z012510 Z011510 D022110 D022130 D021110 D021130 LG color tv Circuit Diagram schematics texas ttl YJ 162A Texas Instruments TTL integrated circuits catalog SN74180 AC digital voltmeter using 7107 Sii 9024 MC3123 sn74ls860 SN7490AJ sn74243

    Untitled

    Abstract: No abstract text available
    Text: 112 CONNECTION DIAGRAM P IN O U T A 54S/74S112 t1" 00 \/&4LS/74LS112 b DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP DESCRIPTION — The '112 features individual J, K, C lo ck and asynchronous Set and C lear inputs to each flip-flop. When the clo ck goes HIGH, the inputs


    OCR Scan     		PDF 54S/74S112 4LS/74LS112 54/74LS 54/74S

    SN7401

    Abstract: sn29601 SN7449 SN74298 SN74265 MC3021 SN54367 sn74142 signetics 8223 9370c
    Text: INDEX PAGE TTL Integrated Circuits Mechanical Data 1 TTL Interchangeability Guide 6 Functional Selection Guide 19 Explanation of Function Tables 38 54/74 Families of Compatible TTL Circuits 40 TTL INTEGRATED CIRCUITS MECHANICAL DATA J ceramic dual-in-line package


    OCR Scan     		PDF 24-lead SN74S474 SN54S475 SN74S475 SN54S482 SN74S482 LCC4270 SN54490 SN74490 SN54LS490 SN7401 sn29601 SN7449 SN74298 SN74265 MC3021 SN54367 sn74142 signetics 8223 9370c

    LS112A

    Abstract: SN54LS112 SN54LS112A SN54S112 SN74 SN74LS112A SN74S112A
    Text: SN5 4 L S 112A, SN5 4 S 112, SN7 4 L S 112A, SN7 4 S 112A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP FLOPS WITH PRESET AND CLEAR D 2 6 6 1 . A P R IL 1 9 8 2 - R E V IS E D M A R C H 1 9 8 8 Fully Buffered to Offer Maximum Isolation from External Disturbance S N 5 4 L S 1 1 2 A . S N 5 4 S 1 1 2 . . . J OR W P A C K A G E


    OCR Scan     		PDF SN54LS112A, SN54S112, SN74LS112A, SN74S112A LS112A SN54LS112 SN54LS112A SN54S112 SN74 SN74LS112A

    Untitled

    Abstract: No abstract text available
    Text: R C H U - P S E M IC O N D U C T O R tm DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary


    OCR Scan     		PDF DM74LS112A