74AS112
Abstract: DM54AS1121DM74AS112 S112
Text: DM54AS 112/ DM74AS 112 PRELIMINARY %9A National ÆjA Semiconductor 54AS1121DM74AS112 Dual J-K Negative-EdgeTriggered Flip-Flops with Preset and Clear General Description Features The 0M 54AS112 is a dual edge-triggered flip -flo p . Each flip -flo p has individual J, K, c lo c l^ c le a r and preset inputs,
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DM54AS1121DM74AS112
0M54AS112
DM54AS112
DM74AS112
TL/F/6285-2
74AS112
S112
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SN54ALS112A
Abstract: SN74ALS112A SN74AS11
Text: TYPES SN54ALS112A, 54AS112, SN74ALS112A, SN74AS112 TYPES n e g a TIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET D 2 6 6 1 , APRIL 19 8 2 —REVISED DECEMBER 1 9 8 3 Fully Buffered to O ffer Maxim um Isolation from External Disturbance SN54ALS112A, S N 54AS112
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SN54ALS112A,
SN54AS112.
SN74ALS112A,
SN74AS112
D2661,
1982-REVISED
ALS112A
AS112
SN54ALS112A
SN74ALS112A
SN74AS11
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74AS112
Abstract: LS112AM
Text: TYPES SN54ALS112A, 54AS112, SN74ALS112A, SN74AS112 DUAL J K NEGATIVE EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET D 2 6 6 1 , A P R IL 1 9 8 2 - R E V I S E D D E C E M B E R 1 9 8 3 • Fully Buffered to Offer Maximum Isolation from External Disturbance
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SN54ALS112A,
SN54AS112,
SN74ALS112A,
SN74AS112
54ALS112A,
54AS112
LS112A
74AS112
LS112AM
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