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    Texas Instruments 54AC11030J

    NAND GATE; Temperature Grade: MILITARY; Terminal Form: THROUGH-HOLE; No. of Terminals: 14; Package Code: DIP; Package Shape: RECTANGULAR;
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    54AC11030 Datasheets (4)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    54AC11030 Texas Instruments 8-INPUT POSITIVE-NAND GATES Original PDF
    54AC11030 Texas Instruments 8-INPUT POSITIVE-NAND GATES Original PDF
    54AC11030FK Texas Instruments 8-INPUT POSITIVE-NAND GATE Original PDF
    54AC11030J Texas Instruments 8-INPUT POSITIVE-NAND GATE Original PDF

    54AC11030 Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    Untitled

    Abstract: No abstract text available
    Text: 54AC11030, 74AC11030 8ĆINPUT POSITIVEĆNAND GATES ą ą SCAS001A − JUNE 1987 − REVISED APRIL 1993 • • • • • 54AC11030 . . . J PACKAGE 74AC11030 . . . D OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations


    Original     		54AC11030, 74AC11030 SCAS001A 54AC11030 500-mA 300-mil PDF

    54AC11030

    Abstract: 74AC11030
    Text: 54AC11030, 74AC11030 8-INPUT POSITIVE-NAND GATES SCAS001A – JUNE 1987 – REVISED APRIL 1993 • • • • • 54AC11030 . . . J PACKAGE 74AC11030 . . . D OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations


    Original     		54AC11030, 74AC11030 SCAS001A 54AC11030 500-mA 300-mil 54AC11030 74AC11030 PDF

    54AC11030

    Abstract: 74AC11030
    Text: 54AC11030, 74AC11030 8-INPUT POSITIVE-NAND GATES SCAS001A – JUNE 1987 – REVISED APRIL 1993 • • • • • 54AC11030 . . . J PACKAGE 74AC11030 . . . D OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations


    Original     		54AC11030, 74AC11030 SCAS001A 54AC11030 500-mA 300-mil 54AC11030 74AC11030 PDF

    54AC11030

    Abstract: 74AC11030
    Text: 54AC11030, 74AC11030 8ĆINPUT POSITIVEĆNAND GATES ą ą SCAS001A − JUNE 1987 − REVISED APRIL 1993 • • • • • 54AC11030 . . . J PACKAGE 74AC11030 . . . D OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations


    Original     		54AC11030, 74AC11030 SCAS001A 54AC11030 500-mA 300-mil 54AC11030 74AC11030 PDF

    Untitled

    Abstract: No abstract text available
    Text: 54AC11030, 74AC11030 8-INPUT POSITIVE-NAND GATES D2957. JUNE 1987-R E V IS E D APRIL 1993 Flow-Through Architecture Optimizes PCB Layout Center-Pin Vqc and GND Configurations Minimize High-Speed Switching Noise EPIC'“ Enhanced-Pertormance Implanted CMOS 1-^m Process


    OCR Scan     		54AC11030, 74AC11030 D2957. 1987-R 500-mA 300-mll S4AC11032-85 54AC11030 D2957, PDF

    Untitled

    Abstract: No abstract text available
    Text: 54AC11030, 74AC 11030 8-INPUT POSITIVE-NAND GATES TI0058— 0 2 9 5 7 , JUNE 1987— REVISED MAR CH 1990 54AC11030 . . . J PACKAGE 74AC11030 . . . D OR N PACKAGE Flow-Through Architecture to Optimize PCB Layout TOP VIEW Center-PIn V c c and GND Configurations to


    OCR Scan     		54AC11030, TI0058-- 500-mA 300-mil 54AC11030 74AC11030 74AC11030 D2957, PDF

    54AC11030

    Abstract: 74AC 74AC11030 D2957
    Text: 54AC11030, 74AC11030 8-INPUT POSITIVE-NAND GATES T I0 0 5 8 — D 2 9 5 7 , J U N E 1 9 8 7 — R E V IS E D M A R C H 1 9 9 0 Flow-Through Architecture to Optimize PCB Layout 54AC11030 . . . J PACKAGE 74AC11030 . . . D OR N PACKAGE TOP VIEW Center-Pin V q c and GND Configurations to


    OCR Scan     		54AC11030, TI0058â D2957, 500-mA 300-mil 54AC11030 TI0058 74AC 74AC11030 D2957 PDF

    Untitled

    Abstract: No abstract text available
    Text: 54AC11030, 74AC11030 8-INPUT POSITIVE-NAND GATES D2957, JUNE 1987 - REVISED APRIL 1993 Flow-Through Architecture Optimizes PCB Layout 54AC11030. . . J PACKAGE 74AC11030 . . . D OR N PACKAGE TOP VIEW Center-Pin Vcc and QND Configurations Minimize High-Speed Switching Noise


    OCR Scan     		54AC11030, 74AC11030 D2957, 500-mA 300-mil 54AC11030 1967-REVISED PDF

    54AC11030

    Abstract: 54ACT11030 74AC11030 74ACT11030 D2957
    Text: 54ACT11030, 74ACT11030 8-INPUT POSITIVE-NAND GATES TI0059— D2957, MARCH 1987— REVISED M ARCH 1990 54A C T11030 I PACKAGE 74ACT11030 . . . D OR N PACKAGE Inputs are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout TOP VIEW Center-Pin V q c and GND Configurations to


    OCR Scan     		54ACT11030, 74ACT11030 TI0059â D2957, 500-mA 300-mil 54ACT11030 54AC11030 74AC11030 74ACT11030 D2957 PDF

    Untitled

    Abstract: No abstract text available
    Text: 54ACT11030, 74ACT11030 8-INPUT POSITIVE-NAND GATES TI0059— D2957, MARCH 1987— REVISED MARCH 1990 54ACT11030 . . . J PACKAGE 74ACT11030 . . D OR N PACKAGE • Inputs are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout TOP VIEW


    OCR Scan     		54ACT11030, 74ACT11030 TI0059-- D2957, 500-mA 300-mil 54ACT11030 74ACT11030 JL15V PDF