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    ADDON TKD4580-50-PI-AO

    ARRIS TKD4580-50-PI COMP TAA SFP LC XCVR
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    NAC TKD4580-50-PI-AO 3 1
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    50PIA Datasheets Context Search

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    Untitled

    Abstract: No abstract text available
    Text: HM-65162 33 HARRIS 2048 x 8 Asynchronous CMOS Static RAM Features Pinouts DIP • Fast Access T im e . 55 /7 0 /9 0 n s M ax. • Low Standby C u rre n t. TO P VIEW 50piA M ax.


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    PDF HM-65162 50piA

    Untitled

    Abstract: No abstract text available
    Text: r r i m LTC1426 m TECHNOLOGY Micropower Dual 6-Bit PWM DAC F€OTUR€S D€SCRIPTIOn • Wide Supply Range: 2.7V < V^c ^ 5.5V ■ Wide Reference Voltage Range: OV to 5.5V The LTC 1426 is a dual micropower 6-bit PWM DAC featuring versatile PWM outputs and aflexible pushbutton


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    PDF LTC1426 LTC1426 1329/LTC1329-10/LTC1329-50 LTC1446/LTC1446L LTC1451/LTC1452/LTC1453 LTC1590 LTC8043 16-pin 12-Bit

    Untitled

    Abstract: No abstract text available
    Text: w GEC PLESSEY ADVANCE INFORMATION S E M I C O N D U C T O R S D.S. 3931 1.5 SP5654 2.7GHz 3-WIRE BUS CONTROLLED SYNTHESISER The SP5654 is a single chip frequency synthesiser designed for satellite TV tuning systems. It is a programming variant of the SP5655 allowing the design of one tuner with


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    PDF SP5654 SP5654 SP5655 divide-by-16 100kHz) 37bflS52

    Untitled

    Abstract: No abstract text available
    Text: 74LS260, S260 Signetics Gates Dual 5-Input NOR Gate Product Specification Logic Products TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT TOTAL 74LS260 9ns 4 mA 74S260 4ns 22mA FUNCTION TABLE OUTPUT INPUTS A B c E Y H X X X X L X H X X X L X X H X X


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    PDF 74LS260, 74LS260 74S260 SO-14 N74S260N, N74LS260N N74LS260D, N74S260D 74Srting 1N916,

    IC 74175

    Abstract: pin diagram of ic 74175 74ls175 pin diagram 74175 DIP ic 74175 pin diagram quad D flip-flop 74175 pin D flip-flop 74175 pin pin configuration 74175 N74LS175D 74ls175
    Text: 74175, LS175, S 175 Flip-Flops S ig n e lic s Quad D Flip-Flop Product Specification Logic Products FEATURES • Four edge-triggered D flip-flops • Three speed-power ranges available • Buffered common clock • Buffered, asynchronous Master Reset TYPE


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    PDF LS175, 74LS175 74S175 35MHz 40MHz 110MHz SO-16 1N916, 1N3064, 500ns IC 74175 pin diagram of ic 74175 74ls175 pin diagram 74175 DIP ic 74175 pin diagram quad D flip-flop 74175 pin D flip-flop 74175 pin pin configuration 74175 N74LS175D

    2N5326

    Abstract: OTC2220 OTC2420 SVT60-5 SVT80-5
    Text: OPTEK TE CH N O L O G Y INC 4flE D • bV T& Sa D □□G13ût. SST ■ OTK Product Bulletin OTC2420 August 1990 High Speed NPN Switching Transistor Die Type OTC242Q 80V, 5A Applications • Low Voltage Inverters • Pulse Amplifiers • Base Drive Circuits


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    PDF OTC2420 OTC2220 2420-80L 3-80H 2420-60H 500mA 2N4305-2N4311, 2N5326, 2N5326 OTC2220 SVT60-5 SVT80-5

    Untitled

    Abstract: No abstract text available
    Text: MX23C1B10 1 6 M -B IT T aM x 8 / 1 M X I B ] CM O S M A SK ROM FEATURES • • • • • Switchable configuration - 2M x 8 byte mode - 1 M x 16(word mode) • Single +5V power supply • Fast access time: 100/120/150/200ns (max) • Totally static operation


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    PDF MX23C1B10 100/120/150/200ns 50piA 16M-bit, 100/120/150/200ns. simX23C161OTC-10 MX23C1610RC-10 MX23C1610PC-12 MX23C161OMC-12 MX23C161OTC-12

    Untitled

    Abstract: No abstract text available
    Text: CMOS MASK ROM KM23C8100A 8M-Bit 1M X 8 /5 1 2 K X 16 CMOS MASK ROM FEATURES GENERAL DESCRIPTION • S w itc h a b le o rg a n iz a tio n The KM23C8100A is a fully static mask programmable ROM fabricated using silicon gate CMOS process technology, and is organized either as 1 ,0 4 8 ,5 7 6 X 8 bit


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    PDF KM23C8100A KM23C8100A 50piA KM23C8100A) KM23C8100AG)

    74ls112 pin diagram

    Abstract: 74ls112 pin configuration 74LS112 N74S112D 74ls112 function table
    Text: 7 4 LS1 1 2 , S 1 1 2 Flip-Flops S ig n e t ic s Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION The '112 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, Clock, Set and_Reset inputs. The Set So and Reset (R d) inputs, when LOW,


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    PDF 1N916, 1N3064, 500ns 500ns 74ls112 pin diagram 74ls112 pin configuration 74LS112 N74S112D 74ls112 function table

    7L Marking

    Abstract: No abstract text available
    Text: LT1579 300mA Dual Input Smart Battery Backup Regulator F€flTUR€S D€SCRIPTIOfl • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ The LT 1579 is a dual input, single output, low dropout regulator. This device is designed to provide an uninterruptible output voltagefrom two independent input


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    PDF LT1579 300mA 50piA 24-Lead 7L Marking

    SVT60-5

    Abstract: 2N5326 OTC2220 OTC2420 OTC242Q svt80 SVT60
    Text: b7^asaa 4flE D OPTEK TECHNOLOGY INC oaoiBfit, I OTK sst ü g jjU H b K Product Bulletin OTC2420 August 1990 " T Z G - »«1 High Speed NPN Switching Transistor Die Type OTC242Q 80V, 5A Applications • Low Voltage Inverters • Pulse Amplifiers • Base Drive Circuits


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    PDF OTC2420 OTC242Q OTC2220 2420-80L 2420-60L 2420-80H 2420-60H 500mA 2N4305-2N4311, SVT60-5 2N5326 OTC2220 svt80 SVT60

    km681000clg-7l

    Abstract: KM681000CLP-7 KM681000CLT-5L KM681000CLP-7L KM681000CLG KM681000C
    Text: KM681000C Family CMOS SRAM 128K x8 bit Low Power CMOS Static RAM FEATURES G ENERAL DESCRIPTION • Process Technology: Q.4ftm C M O S • Organization: 128Kx8 • Power Supply Voltage : Single 5.0V±1Q% • Low Data Retention Voltage : 2V Mln • three state output and TTL Compatible


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    PDF KM681000C 128Kx8 32-DIP-600, 32-SOP-52S, 32-TSOP1-0820F/R KM681000CL KM6B1000CL-L KM681000CLI km681000clg-7l KM681000CLP-7 KM681000CLT-5L KM681000CLP-7L KM681000CLG

    BIPD

    Abstract: No abstract text available
    Text: DATA SHEET NEC / MOS INTEGRATED CIRCUIT / ffP P 4264165, 4265165 64 M-BIT DYNAMIC RAM 4 M-WORD BY 16-BIT, HYPER PAQE MODE EDO , BYTE READ/WRITE MODE D escription The /iPD4264165,4265165 are 4,194,304 words by 16 bits CMOS dynamic RAMs with optional hyper page mode


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    PDF 16-BIT, uPD4264165 50-pin jjPD4264165-A50 jjPD4265165-A50 /jPD426416S-A60 iPD4265165-A60 -60-7JF PD4264165, 426St65 BIPD