Contextual Info: 00 00 00 O Ö O D a O a I I I 1 00 00 I •p>. I I r~ 1 r~ I iI I r~ I r* II I o CO -vl | O w CD cn 00 ■t*. cn o O CO I l 00 o 00 CO 00 cn cn Ol 05 O CD cn CO 00 O 00 ICD I- CD D CO CO CD CD 00 i I c_ Serial Entry ■P». Parallel Entry No. of Bits i~ I

i.c. cmos 4514b

Abstract: 4514B 45148 D 4515 4000B 4515B
Contextual Info: 4514B 4515 B INTERNATIONAL, INC CMOS 4-T0-16 LINE DECODERS WITH LATCH FEA TU R ES ♦ Strobed Input Latch ♦ Inhibit Control ♦ Selected Output Active High 4514B or Active Low (4S15B) D ESC RIPTIO N The 45146 and 4515B are two out­ put options of a 4-to-16 Lin« Decoder with