MN4514BS

Abstract: MN4000B MN4514B
Contextual Info: M 4514B/M 4514BS CMOS Logic MN4000B Series M 4514B M 4514BS 4 - B i t L a t c h / L i n e D e c o d e r s High • Description The M N 4514B/S are d e co d e rs w h ic h c o n v e rt 4-bit in p u t to 16-bit o u tp u t w ith th e fu n c tio n o f la tc h in g th e in p u t d a ta .

Contextual Info: COS/MOS INTEGRATED CIRCUITS _ n 4 ^ /+ » ‘¡ ¡ S Ä 4-BIT LATCH/4-TO-16 LINE DECODER: HCC/HCF 4514B OUTPUT "H IG H" ON SELECT HCC/HCF 4515B OUTPUT "LOW" ON SELECT • • • • • • Q UIESCENT C U R R E N T SPECIFIED TO 2 0 V FOR HCC D EVICE STRO BED INPUT LATC H

Contextual Info: b llò / m u ò S G S “ T H 0 ,V ,S 0 N D 7C IM TFRRATFil L. - a . « CIRCUITS 7929225 ß I ? c >2 ^ 2 3 7 ^ I o o i^ a ? a | ^ HCG/HCF 4515B-A — ✓ j . i S G S S EM IC O N D U C T O R C O R P 4-BIT L A TCH/4-T0-16 LIN E DECODER: HCC/HCF 4514B OUTPUT "HIGH" ON S ELE C T

Contextual Info: R&E 4514B 4515B INTERNATIONAL, INC. CMOS 4-T0-16 LINE DECODERS WITH LATCH FEATURES ♦ ♦ ♦ Strobed Input Latch Inhibit Control Selected Output Active High 4514B or Active Low (4515B) DESCRIPTION 1 TRUTH TABLE (Strobe - 1) Data Inputs Selected Output

Contextual Info: 4514B l-OF-16 DECODER/DEMULTIPLEXER WITH INPUT LATCH D E S C R IP T IO N — T he 4 5 1 4 B is a 1-of-16 D eco d er/D em ultiplexer w ith fo u r b in ary weighted Address Inputs A 0 - A 3 , a La tc h Enable In p u t ( E L ) , an active LO W Enable In p u t (E ) and sixteen m utu ally

i.c. cmos 4514b

Abstract: an 7164 1765D
Contextual Info: " I l f ih itn ìììllT fÌ ^ " ^ ^ GOLDSTAR TECHNOLOGY 4 0 2 8 7 5 7 GOLDSTAR TECHNOLOGY INC-. D4E D | MGSÖ7S7 0DD17hS 2 04E I NC. 0 17 65 D T - b l- H 'S ! 4514B l-O F -16 DECODER/DEMULTIPLEXER WITH INPUT LATCH D E S C R IP T IO N — The 4514B Is a 1*of-16 Decoder/Dem ultiplexer w ith fo u r binary weighted Address

4514B

Abstract: D 4515 4000B 4515B 4T016 AICB
Contextual Info: 4514B 4515B INTERNATIONAL, INC. CMOS 4-T0-16 LINE DECODERS WITH LATCH FEATURES ♦ ♦ ♦ Strobed Input Latch Inhibit Control Selected Output Active High 4514B or Active Low (4515B) DESCRIPTION CONNECTION DIAGRAM (all packages) D ata Inputs Vqd The 4514B and 4515B are two out*

Contextual Info: R&E 4514B 4515B INTERNATIONAL, INC. CMOS 4-T0-16 LINE DECODERS WITH LATCH FEATURES ♦ ♦ 4 Strobed Input Latch Inhibit Control Salactad O utput Activa High 4514B or Activa Low (4515B) DESCRIPTION The 4514B and 4515B are two out­ put options o f a 4-to -16 Line Decoder w ith

kcc CL-60

Abstract: transistor hh 004 circuits diagram transistor d 4515
Contextual Info: b llò / m u ò S G S “ T H 0 ,V ,S 0 N D 7C ß IM TFRRATFil L. - a . « I ? c >2 ^ 2 3 7 ^ C IR C U IT S I ^ o o i^ a ? | HCG/HCF 4515B-A — 7929225 a ✓ j . i S G S SEMICONDUCTOR CORP 4 -B IT LA T C H /4 -T 0 - 1 6 L IN E DEC O D ER: H C C /H C F 4514B O U T P U T " H IG H " ON SELECT

i.c. cmos 4514b

Abstract: 4514B 45148 D 4515 4000B 4515B
Contextual Info: 4514B 4515 B INTERNATIONAL, INC CMOS 4-T0-16 LINE DECODERS WITH LATCH FEA TU R ES ♦ Strobed Input Latch ♦ Inhibit Control ♦ Selected Output Active High 4514B or Active Low (4S15B) D ESC RIPTIO N The 45146 and 4515B are two out­ put options of a 4-to-16 Lin« Decoder with

N23A

Abstract: circuits of cd4514 mc14514 CD4514BC CD4514BCN CD4514BCWM CD4515BC M24B MC14515 MS-013
Contextual Info: Revised January 1999 EMICONDUCTGRTM 4514BC« CD4515BC 4-Bit Latched/4-to-16 Line Decoders General Description Features T he C D 4514BC and C D 4515BC are 4-to-16 line decoders w ith latched inputs im plem ented with com plem entary MOS CMOS circuits constructed with N- and P-channel

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MCI 4514B MCI 4515B 4-Bit Transparent Latch/4-to-16 Line Decoder The 4514B and MC14515B are two output options of a 4 to 16 line decoder with latched inputs. The 4514B output active high option presents a logical “1” at the selected output, whereas the MC14515B (output

CD4514BC

Abstract: CD4514BCN CD4514BCWM CD4515BC M24B MC14514 MC14515 MS-013 N24A
Contextual Info: Revised Ja nuary 1999 S E M I C O N D U C T O R TM 4514BC« CD4515BC 4-Bit Latched/4-to-16 Line Decoders Features • W ide supply voltage range: The C D 4514BC output active high option presents a logi­ cal “ 1” at the selected output, w hereas the C D 4515BC pre­

sot94

Abstract: HEF4514BP
Contextual Info: 4514B MSI 1-OF-16 DECODER/DEMULTIPLEXER WITH INPUT LATCHES The H E F 4514B is a 1-of-16 d e co d e r/d e m u ltip le xe r, having fo u r b in a ry w eighted address inputs A g to A 3 , a latch enable in p u t (E L ), and an active LOW enable in p u t (E). T he 16 o u tp u ts (Oq to O 1 5 ) are

MN4000B

Contextual Info: PANASONIC INDL/ELEK -CIO de - J hb t^ aase •. CMOS Logic MN4000B Series 6 9 3 2 8 5 2 PANASONIC I N O L t l L E C T R O f f r C - □□ascm t | - .: ' : M N 4514 B /M N 4514 BS 66C 05093 D' T -67-11-51 M N 4514B/M N 4514BS 4 - B it L a t c h / L i n e Decoders High

transistor D 4515

Abstract: ci 4514 a 4514 v D 4515 4514 4514 decoder Transistor 4515 4514B 4515B
Contextual Info: COS/MOS I WTPPDÄTFn IN T E b R A T h U A .S I4 -& ^ HCC/HGF 4514B HCC/HCF 4515B CIRCUITS 4 -B IT L A T C H /4 -T O -1 6 LIN E DECODER: H CC /H CF 4514B O U T P U T "H IG H " ON SELECT HCC /H CF 4 5 1 5B O U T P U T "LOW " ON SELECT • • • • • •

Contextual Info: TOSHIBA TC74HC4514AP TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC74HC4514AP 4 -TO - 16 LINE DECODER/LATCH The TC74HC4514A are high speed CMOS 4 - LINE TO 16 LINE DECODER WITH LATCHED INPUTs fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent

TC74HC4515P

Contextual Info: TOSHIBA 14E 0 I IGTPEMä GQÌÒb03 S | LOGIC/MEMORY TC74HC4514P_ TC74HC4515P TC74HC4514P 4-T0-16 LINE DECODER/LATCH TC74HC4515P 4-T0-16 LINE DECODER/LATCH INV. The TC74HC4514 and TC74HC4515 a re h ig h speed CMOS 4-LINE TO 16-LINE DECODER WITH LATCHED INPUTS f a b r ic a te d w ith s i l i c o n g a te C MOS tec h n o lo g y . I t a c h ie v e s th e h ig h

Contextual Info: February 1984 Revised February 1999 S E M I C O N D U C T O R TM MM74HC4514 4-to-16 Line Decoder with Latch General Description four select inputs determ ine w hich output will go HIGH pro­ vided the IN H IBIT input is LOW. If th e IN H IBIT input is HIGH all outputs are held LOW thus disabling the decoder.

diode s6 8c

Abstract: 4514BP 24PIN 4514B TC74HC4514AP
Contextual Info: TOSHIBA TC74HC4514AP TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC74HC4514AP 4 - TO - 16 LINE DECODER/LATCH The TC74HC4514A are high speed CMOS 4 - LINE TO 16 LINE DECODER WITH LATCHED INPUTs fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent

Contextual Info: M74HC4514 M74HC4515 SGS-THOMSON iy HC4514:4 TO 16 LINE DECODER/LATCH HC4515: 4 TO 16 LINE DECODER LATCH INV. HIGHSPEED tpD = 18 ns (TYP.) AT Vcc = 5 V LOW POWER DISSIPATION Icc = 4 nA (MAX.) AT Ta = 25 °C HIGH NOISE IMMUNITY V nih = V nil = 28 % Vcc (MIN.)

Contextual Info: R&E 4555B 4556B INTERNATIONAL, INC. CMOS DUAL 2-T0-4 LINE DECODERS FEATURES ♦ Buffered Outputs ♦ Selected Output Active High 4555B or Active Low (45S6B) Expandable ♦ CONNECTION D IA G R A M (all packages) Vd d I 16 DESCRIPTION The 4555 B and 4556B are constructed

Contextual Info: 4518B 4520B INTERNATIONAL, INC. CMOS DUAL UP COUNTERS FEATURES 4 Two Independent 4-B it Counters 4 Internally Synchronous fo r High Speed Dual BCD 4518B and Dual Binary (4520B) Configurations 4 D irect Reset 4 Logic Edge-Clocked Design 4 Trigger from either Edge o f Clock Signal

D 4515

Abstract: 4514B P043A
Contextual Info: HCC/4514B HCC/HCF4515B 4-BIT LATCH/4-TO-16 LINE DECODER HCC/4514B OUTPUT ”HIGH” ON SELECT HCC/HCF4515B OUTPUT ”LOW” ON SELECT . . . . QUIESCENT CURRENT SPECIFIED TO 20V FOR HCC DEVICE STROBED INPUT LATCH INHIBIT CONTROL INPUT CURRENT OF 100nA AT 18V AND 25°C