Untitled
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Text: HITACHI/ LOGIC/ARRAYS/NEM ^2 HD74HC242 HD74HC243 92D 10459 # Quad. Bus Transceivers with 3-state outputs # Quad. Bus Transceivers The HD74HC242 is an inverting bu ffer and the HD74HC243 is a noninverting buffer. DEI 44TbEQ3 OOlOMST b~|~ enable (G BA), and one active low enable (GAB).
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HD74HC242
HD74HC243
0D1D315
T-90-20
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Untitled
Abstract: No abstract text available
Text: HITACHI/ LOGIC/ARRAYS/MEM Ì2 dÊ J 44^303 0D1D44L. A | - HD74HC195 92D 10446 # 4-bit Parallel-Access Shift Register This shift register feetures parallel inputs, parallel outputs, J-K serial inputs, S hift/L oad control input, and a direct | D T- Hb -O l-ß S
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0D1D44L.
HD74HC195
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Untitled
Abstract: No abstract text available
Text: H I T A C H I / LOGIC/ARRAYS/flEH ^5 4 4 ^ 5 0 3 0010b44 1 92D HD 74H C T240 # 10644 D ]~'SZ-<>7 Octal B u ffers/Line D rivers/L ine Receivers with inverted 3-state outputs PIN ARRANGEMENT The HD74HCT240 is an inverting buffer and has two active low enables (1G and 2G). Each enable independently con
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0010b44
HD74HCT240
44TtiED3
0D1D315
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Untitled
Abstract: No abstract text available
Text: Ï Ë J 4 4 cit,2D3 G G 1 D 3 S 7 1 J H I T A C H I / L O G I C / A R R A Y S / N E M "il 92D HD74HC91 üT-ïé-ûf-O 10357 • 8 - bit Shift Register This serial-in, serial-out, 8-bit shift register is composed o f eight R-S master-slave flip-flo ps, inpu t gating, and a clock
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HD74HC91
0D1D315
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Untitled
Abstract: No abstract text available
Text: HITACHI/ LOGIC/ARRAYS/HEfl TS D E | l44^13203 D O l O M h T ; HD74HC257 92D T 10469 D # Quad.2-to- 1-line Data Selectors/Multiplexers with noninverted 3-state outputs) -T -lcH-'LlSl PIN ARRANGEMENT The large output drive capability coupled with the 3-state
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HD74HC257
0D1D315
T-90-20
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Untitled
Abstract: No abstract text available
Text: HITACHI/ L O G IC /A RRAYS/ NEN ^2 D E I 4 4 ^ 5 0 3 GD1D413 4 J ~ 92D HD74HC165 # 10413 Parallel-load 8-bit Shift Register This 8-bit serial shift register shifts data fro m Q A to Q h T-46-09-05 PIN ARRANGEMENT when clocked. Parallel inputs to each stage are enabled by a
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GD1D413
HD74HC165
T-46-09-05
0D1D315
T-90-20
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Abstract: No abstract text available
Text: H IT A C H I/ L O G I C / A R R A Y S /flEd ^2 D E I 44TbE03 D D lD t4 2 92D HD74HCT238 • fi 10642 3-to-8-line Decoder/D em ultiplexer The HD74HCT238 has 3 binary select inputs A, B, and C . if the device is enabled these inputs determined which one of
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44TbE03
HD74HCT238
HD74HCT238
0D1D315
T-90-20
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Untitled
Abstract: No abstract text available
Text: HITACHI/ LOGIC/ARRAYS/MEN T2 DEI 4 4IikiE03 0010404 S > HD74HC298 92D 10484 # Quad. 2-input Multiplexers with storage) PIN ARRANGEMENT This circuit is controlled by the signals word select and clock. When the word select input is taken low w ord 1 (A 1, B i,
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ikiE03
HD74HC298
0D1D315
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Untitled
Abstract: No abstract text available
Text: HITACHI/ L O G I C / A R R A Y S / H E M T 2 HD74HC367 D Ë | MMTba03 001050b 92D 10506 D T - 5 a -0 9 9 Hex Bus Drivers noninverted Data Outputs with 3-state outputs I I PIN ARRANGEMENT • FEATURES • High Speed Operation: tpe/ (A to Y)=8.5ns typ. (Q_=50pF)
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HD74HC367
MMTba03
001050b
0D1D315
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Untitled
Abstract: No abstract text available
Text: HITACHI/ L O G I C / A RR AYS/ HE M TE HD74HC620 HD74HC623 % D E | 44Tt>203 0Q1QSS7 t> 92D 10557 o T 'S Z 'S l # Octal Bus Transceivers with inverted 3-state outputs Octal Bus Transceivers (with 3-state outputs) This octal bus transceiver is designed for asynchronous twoway com munication between data buses. The control
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HD74HC620
HD74HC623
0D1D315
T-90-20
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Untitled
Abstract: No abstract text available
Text: H I T A C H I / LOGIC/ARRAYS/riEfl TE D Ê | 4 4^^5 03 0 □ 1 □ 4 01 ô |~~ 92D HD74HC155 # 10401 D T 'iû ^ - a i >55" Dual 2-to-4-line Decoders/Dem ultiplexers This circuit features dual 1-line-to-4-line dem ultiplexer with | I PIN ARRANGEMENT individual strobes and common binary-address input. When
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HD74HC155
44TtiED3
0D1D315
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Untitled
Abstract: No abstract text available
Text: HITACHI/ L O G I C / A R R A Y S / M E M 12 HD74HC157 HD74HC158 B E I 4iHbaG3 0P104CI3 1 | ~ . 92D 1 04 03 D 7 ^ 7 -.2 /-£ / # Quad. 2-to-1-line Data Selectors/Multiplexers with noninverted outputs # Quad. 2-to-l-line Data Selectors/Multiplexers (with inverted outputs)
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HD74HC157
HD74HC158
0P104CI3
44TtiED3
0D1D315
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Untitled
Abstract: No abstract text available
Text: HITACHI/ L O G I C / A RR AYS/ ME M ^5 DÊ] DfllGMhB fl 92D HD74HC245 # D T 'S % '3 f 10463 Octal Bu s Transceivers with 3-state outputs Each device has an active low enable input G and a direction control input, D IR . When D IR is high, data flows from the
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HD74HC245
0D1D315
T-90-20
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R40 AH
Abstract: No abstract text available
Text: HM5283206 Series 131,072-word x 32-bit x 2-bank Synchronous Graphic RAM HITACHI ADE-203-223A Z Rev. 1.0 May. 30, 1996 Description All inputs and outputs signals refers to the rising edge of the clock input. The HM5283206 provides 2 banks to realize better performance. 8 column block write function and write per bit function are
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HM5283206
072-word
32-bit
ADE-203-223A
Hz/83
Hz/66
z//77////////a
QQ27flfl2
R40 AH
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Abstract: No abstract text available
Text: HITACHI/ LOGIC/ARRAYS/HEM HD74HC258 TE D eJ 4 4 ^ 2 0 3 # D01D471 92D 7 10471 D Quad.2-to-l-line Data Selectors/Multiplexers with 3-state outputs) "t* -iô”7 *• 2 , 1 - 5 / The large o u tp u t drive capability coupled w ith the 3*state feature make this device ideal fo r interfacing w ith bus lines
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HD74HC258
D01D471
44TtiED3
0D1D315
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Abstract: No abstract text available
Text: HITACHI/ LOGIC/ARRAYS/HEM T5 " HD74HC423A D Ë J 44Tti5G3 D D l D S a S " # “ 92D 4 10525 D Preliminary Dual Retriggerable Monostable Multivibrators T h is m ultivibrator features output-pulse-duratlon control by two methods. The basic pulse duration is programmed by
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HD74HC423A
44Tti5G3
0D1D315
T-90-20
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Untitled
Abstract: No abstract text available
Text: H I T A C H I / L O G I C / A R R A Y S / M E M IS » Ë J 44StaD3 GDIDSHI 7 92D H D 74H C390 # D T -* i5 -2 3 -/3 10521 Dual Decade Counters The HD74HC390 incorporate dual decade counters, each | PIN ARRANGEMENT composed o f a div!de-by-two and a divide-by-five counter.
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44StaD3
HD74HC390
divide-by-100
0D1D315
T-90-20
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Untitled
Abstract: No abstract text available
Text: HITACHI/ L O G I C / A R R A Y S / M E M TE D Ë | 44 ciL.2a3 D D l D S l b 92D H D 74H C 375 • 3 D 10516 T-46-07-09 Quad. Bistable Latches Th is latch is ideally suited fo r use as tem porary storage fo r | PIN ARRANGEMENT binary inform ation between processing units and input/
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T-46-07-09
44TtiED3
0D1D315
T-90-20
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Untitled
Abstract: No abstract text available
Text: H I T A C H I / L O G I C / A R R A Y S / N E M TE »ËJ 4 4 ^ 5 0 3 92D HD74HC09 0010320 10328 d T 'V 3 '^ / # Quad. 2-input AND Gates with open drain outputs I PIN ARRANGEMENT • FEATURES • High Speed Operatlon;-fp iy-8ns ty p . (C i.-5 0 p F ) • High O u tput C u rre n t: Fanout of 10 L S T T L Loadi
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HD74HC09
44TtiED3
0D1D315
T-90-20
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Untitled
Abstract: No abstract text available
Text: HITACHI/ L O G I C / A R R A Y S /NEU lâ D Ê J 4 4 ^ 5 0 3 001054b 92D HD74HC592 • register feeding an 8-bit binary counter. and the counter have - individual | PIN ARRANGEMENT Both the register positive edge-triggered Expansion is easily accomplished by connecting
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001054b
HD74HC592
44TtiED3
0D1D315
T-90-20
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Untitled
Abstract: No abstract text available
Text: HITACHI/ L0GIC/ARRAYS/HEP1 TE D E # 44Tb203 □010534 S 92D HD74HC563,HD74HC573 * When the latch enable LE inpu t is high, the Q outputs o f HD74HC563 w ill fo llo w the inversion o f the D inputs and £ 10 53 4 D T-46 -0 7 -1 1 Octal Transparent Latches
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44Tb203
HD74HC563
HD74HC573
HD74HC573
HD74HC563
0D1D315
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Untitled
Abstract: No abstract text available
Text: HITACHI/ LOGIC/ARRAYS/MEM HD74HCT620 HD74HCT623 im plem entation De | 4m tBD3 O D l Q b U 1 7 I • Octal Bus Transceivers with inverted 3 -state outputs) • Octal Bus Transceivers (w ith 3 -state outputs) This octal bus transceiver is designed fo r asynchronous tw oway com m unication between data buses. The control func
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HD74HCT620
HD74HCT623
0D1D315
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Untitled
Abstract: No abstract text available
Text: HB56UW472EJNB Series, HB56UW464EJNB Series 4.194.304-word x 72-bit High Density Dynamic RAM Module 4.194.304-word x 64-bit High Density Dynamic RAM Module HITACHI ADE-203-723A Z Rev.1.0 Feb. 20, 1997 Description The HB56UW472EJNB, HB56UW464EJNB belong to 8 Byte DIMM (Dual In-line Memory Module)
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HB56UW472EJNB
HB56UW464EJNB
304-word
72-bit
64-bit
ADE-203-723A
HB56UW472EJNB,
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Abstract: No abstract text available
Text: HM5117800 Series 2,097,152-word x 8-bit Dynamic RAM HITACHI ADE-203-632C Z Rev. 3.0 Feb.24,1997 Description The Hitachi H M 5117800 is a CMOS dynamic RAM organized 2,097,152-word x 8-bit. It employs the most advanced CMOS technology for high performance and low power. The H M 5117800 offers Fast Page
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HM5117800
152-word
ADE-203-632C
28-pin
ns/60
ns/70
mW/550m\V/495
HM5117800-5
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