A7s TRANSISTOR

Abstract: Transistor a7s
Contextual Info: ^ Tex as In s t r u m e n t s CD4001B , CD4002B, C D 4025B Types Data sheet acquired from Harris Sem iconductor S C H S015 CMOS NOR Gates Features: • Propagation delay time = 60 ns typ. at C(_ = 50 pF, V d d = 1 0 V ■ Buffered inputt and outputs » Standardized symmetrical output characteristics

4023B

Abstract: 4068B 4012B 4 bit ALU 40118 fairchild 927 4 bit parity generator 8 bit subtractor 4068b 8-soic GI 312
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-CMOS C2 4023B C1 4011B 10 9 8 14 13 12 1 2 3 11 10 9 8 I5 J 1 2 3 4 5 6 7 „TP, 4 5 6 7 10 9 8 6 7 's s C4 4068B C3 4012B 14 13 12 11 10 9 12 8 -at! 1 2 3 12 6 4 U 10 < 7 C5 4001B 3 11 C6 4025B 10 9 E 14 13 1 11

4069UB

Abstract: 4069UB fairchild 4073B 4007UB 4086B 4093B 4049B 40098B 40097B 4041B
Contextual Info: FAIRCHILD DIGITAL CMOS SSI FUNCTIONS Cont’d Item A Function Logic/Connection Diagram DEVICE NO. NOR Gates Package(s) \ 3I.6A.9A 1 Quad 2-Input NOR 4001B C5 2 Triple 3-Input NOR 4025B C6 3I.6A.9A 4002B C7 " 3H6A.9A 4078B 08 3I.6A.9A ( C9 ) • 3I.6A.9A

40097B

Abstract: 4070B 4069UB fairchild 4030B 4085B 40098B 4041B 4069UB
Contextual Info: FAIRCHILD DIGITAL CMOS SSI FUNCTIONS Cont’d Item A Function Logic/Connection Diagram DEVICE NO. NOR Gates Package(s) \ 3I.6A.9A 1 Quad 2-Input NOR 4001B C5 2 Triple 3-Input NOR 4025B C6 3I.6A.9A 4002B C7 " 3H6A.9A 4078B 08 3I.6A.9A ( C9 ) • 3I.6A.9A

4073BP

Abstract: 4073B 4072B 4075B 4069UB
Contextual Info: FAIRCHILD DIGITAL C M O S SSI FUNCTIONS Cont’d Item A Function Logic/Connection Diagram DEVICE NO. NOR Gates Package(s) \ 3I.6A.9A 1 Quad 2-Input NOR 4001B C5 2 Triple 3-Input NOR 4025B C6 3I.6A.9A 4002B C7 " 3H6A.9A 4078B 08 3I.6A.9A 3~ Dual 4-Input NOR~

CD4000B Family specifications

Abstract: CD4001B CD4000B 5Cs transistor 15-V CD4002B CD4025B RCA-CD4000 5Cs transistor 5cs 58
Contextual Info: CD4000B, CD4001B, CD4002B, C D 4025B Types Features: CMOS NOR Gates • High-Voltage Types 2 0 -V o lt Rating ■ ■ ■ ■ Dual 3 In put plus Inverter — C D 4000B Quad 2 In put — C D 4001B Dual 4 In p u t — C D 400 2B T rip le 3 In p u t - C D 402 5B

MN4025B

Contextual Info: CMOS Logic MN4000B Series 4025B/4025BS 4025B / 4025BS T r ip le 3-Input NOR Gates • Description The M N 4025B/S are positive 3-input NOR gates and have 3 circuits in a package. The o u tp u ts are fully buffered to im prove the propagation characteristics b etw een th e in p u t and o u tp u t w hich are affected

Contextual Info: COS/MOS INTEGRATED o o û < ü O l • • • • • • • • B 4 o o i 6> CIRCUITS NOR GATES: Ç DUAL QUAD DUAL TRIPLE 3 INPUT 2 INPUT 4 INPUT 3 INPUT PLUS IN VER TER HCC/HCF 4000B HCC/HCF 4001B HCC/HCF 4002B HCC/HCF 4025B PR O P AG ATIO N D E L A Y T IM E = 60 ns TYP.) A T C L = 50 pF, V DD= 10V

CI 4001B

Abstract: 4001b 4025B HCF4000B-4001B HCF4000B Family specifications hcf4001b HCF Family 4002B 4000B HCC4000B
Contextual Info: HCC/HCF4000B-4001B HCC/HCF4002B-4025B NOR GATE 4000B–DUAL 3 INPUT PLUS INVERTER 4001B–QUAD 2 INPUT 4002B-DUAL 4 INPUT 4025B TRIPLE 3 INPUT . . . . . PROPAGATION DELAY TIME = 60 ns typ. AT CL = 50 pF, VDD = 10 V BUFFERED INPUTS AND OUTPUTS STANDARDIZED SYMMETRICAL OUTPUT

4025B

Abstract: 3 Input NOR gate
Contextual Info: - 4025B T rip le 3 In p u t NOR G ate 47 -

Contextual Info: ADVANCED POW ER Te c h n o l o g y OD OS POWER MOS IV® APT4020BN 400V 26.0A 0.20Í1 4025BN 400V 23.0A 0.25Í1 N-CHANNEL ENHANCEMENT MODE HIGH VOLTAGE POWER MOSFETS MAXIMUM RATINGS All Ratings: Tc = 25°C unless otherwise specified. APT 4020BN APT 4025BN

hcf4001b

Contextual Info: HCC/HCF4000B-4001B HCC/HCF4002B-4025B S G S -T H O M S O N \u NOR GATE 4000B-DUAL 3 INPUT PLUS INVERTER 4001B-QUAD 2 INPUT 4002B-DUAL 4 INPUT 4025B TRIPLE 3 INPUT micropackage. The HCC/HCF4000B, HCC/HCF4001B, HCC/HCF 4002B and HCC/4025B nor gate provide the

4023BE

Abstract: 4001B 4069UB 4025B 4093B 4041B 40097B 4072B 4077B 4002B
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-CMOS C2 4023B C1 4011B 10 9 8 14 13 12 1 2 3 11 10 9 8 I5 J 1 2 3 4 5 6 7 „TP, 4 5 6 7 10 9 8 6 7 's s C4 4068B C3 4012B 14 13 12 11 10 9 12 8 -at! 1 2 3 12 6 4 U 10 < 7 C5 4001B 3 11 C6 4025B 10 9 E 14 13 1 11

CD40258

Abstract: CD4001B CD4002B CD4025B 8y transistor cd4001B HARRIS
Contextual Info: • 44E D HA RR IS S E M I C O N D SE CT OR 4 3 D 2 27 1 0 0 3 7 3 5 2 3 Bi HAS C D 4001B , C D 4002B , C D 4025B Types H A R R IS CMOS NOR Gates F e a tu re s : • Propagation delay time s 60 ns typ. at C l * 50 pF, V q d = 10 V * Buffered inputs and outputs

4060B

Abstract: 4039B 40106B 4017B 4541B 4098B 4536b 4070B 4538B 4013B
Contextual Info: HC/HCT, AC/ACT, VHC/VHCT, LCX, LVQ, LVX, VCX, V2G, V2T, V1G, V1T STANDARD CODE FUNCTION GATE BUFFER CMOS 4000B STANDARD CODE NAND 00, 03, 10, 30, 133 NOR 02, 27, 4002 4000B, 4001B, 4002B, 4025B AND 08, 09, 11, 21 4068B, 4073B, 4081B, 4082B OR 32, 4072, 4075

4025B

Abstract: hcf4001b 4002B 4000B 4001B HCC4000B CI 4001B
Contextual Info: HCC/HCF4000B-4001B HCC/HCF4002B-4025B NOR GATE 4000B–DUAL 3 INPUT PLUS INVERTER 4001B–QUAD 2 INPUT 4002B-DUAL 4 INPUT 4025B TRIPLE 3 INPUT . . . . . PROPAGATION DELAY TIME = 60 ns typ. AT CL = 50 pF, VDD = 10 V BUFFERED INPUTS AND OUTPUTS STANDARDIZED SYMMETRICAL OUTPUT

Contextual Info: ^ Tex a s In s t r u m e n t s C D4001B , CD4002B, C D 4025B Types D ata sheet acquired from H arris Sem iconductor S C H S015 CMOS NOR Gates Features: • Propagation delay time = 60 ns typ. at C(_ = 50 pF, V d d = 10 V a Buffered inputt and outputs > Standardized symmetrical output characteristics

4069UB

Abstract: 40097 40098B 40508 4041B 4583B 40097B 4086B 4007UB 40728
Contextual Info: FAIRCHILD DIGITAL CMOS SSI FUNCTIONS Cont’d DEVICE NO. Function Item Logic/Connection Diagram Package(s) NOR Gates 1 Quad 2-Input NOR 4001B C5 3I.6A.9A 3I.6A.9A 2 Triple 3-Input NOR 4025B C6 3 Dual 4-Input NOR 4002B C7 3I.6A.9A 4 8-Input NOR 4078B 08 3I.6A.9A

4000B

Abstract: 4025B CMOS 4000B series 4000b series CMOS 4000B logic family
Contextual Info: 4025B TRIPLE 3-IN P U T NOR GATE D E S C R IP T IO N — T h is CM O S logic element provides a 3 -input positive N O R function . Th e outputs are fu lly buffered for highest noise im m unity and pattern insensitivity of output impedance. L O G IC A N D C O N N E C T IO N D IA G R A M

Contextual Info: 4025B TRIPLE 3-IN PUT NOR GATE D E S C R IP TIO N — This CMOS logic elem ent provides a 3 -in p u t positive NOR fu n c tio n . The o u tp u ts are fu lly buffe red fo r highest noise im m u n ity and p a tte rn in se n sitivity o f o u tp u t impedance.

4025B

Abstract: HCF4001 B4002 hcf4001b 4002BD
Contextual Info: HCC/HCF4000B-4001 B HCC/HCF4002B-4025B S G S -T H O M S O N * 5 7 NOR GATE 4000B—DUAL 3 INPUT PLUS INVERTER 4001B-QUAD 2 INPUT 4002B-DUAL 4 INPUT 4025B TRIPLE 3 INPUT The HCC/HCF4000B, HCC/HCF4001B, HCC/HCF 4002B and HCC/4025B nor gate provide the system designer with direct implementation of the

CMOS 4000B series device

Abstract: 4001B CMOS HCC 4001B 4002B 4025B cmos b 4xxx HCF Family 025B 4000B hcf025
Contextual Info: COS/MOS INTEGRATED CIRCUITS NO R GATES: • • • • • • • • DUAL QUAD DUAL T R IP L E O O Û £> 4001 & 4 0 0 1 6> 3 2 4 3 IN P U T IN P U T IN P U T IN P U T PLUS IN V E R T E R H CC /H CF 4000B H CC /H CF 4 0 0 1 B H CC /H CF 4002B H CC /H CF 4025B

APT4020BN

Abstract: 4020BN APT4025BN 0504007
Contextual Info: D TO-247 G S POWER MOS IV APT4020BN 400V 26.0A 0.20Ω 4025BN 400V 23.0A 0.25Ω N - CHANNEL ENHANCEMENT MODE HIGH VOLTAGE POWER MOSFETS MAXIMUM RATINGS Symbol VDSS ID All Ratings: TC = 25°C unless otherwise specified. Parameter Drain-Source Voltage

ITE 8721

Abstract: fnd 503 7-segment TAA 2761 A 486 motherboard schematic 3860S 486dx isa bios pin assignment RAS 0510 cxd 9897 tn ti77 k244
Contextual Info: ISA/486 C H |p g . CepyTlgtt N ette S o t t r a e C o p y ñ f tt O 1962, a * « * d T e d » a i e s i e * . l w x M t o n i I C o p y r i i h t O 1992 . Q ñ p » » d T c c t n o f a p B » , ! ^ . A B SIduR am i Poned ib UJ5A. Tw dw u U t h w lw lgim iil