14076B
Abstract: MC14076B MC14076BCP MC14076BD MC14076BDR2
Text: MC14076B 4-Bit D-Type Register with Three-State Outputs The MC14076B 4–Bit Register consists of four D–type flip–flops operating synchronously from a common clock. OR gated output–disable inputs force the outputs into a high–impedance state for use in bus organized systems. OR gated data–disable inputs cause
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MC14076B
MC14076B
r14525
MC14076B/D
14076B
MC14076BCP
MC14076BD
MC14076BDR2
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14076B
Abstract: MC14076B MC14076BCP MC14076BD MC14076BDR2
Text: MC14076B 4-Bit D-Type Register with Three-State Outputs The MC14076B 4–Bit Register consists of four D–type flip–flops operating synchronously from a common clock. OR gated output–disable inputs force the outputs into a high–impedance state for use in bus organized systems. OR gated data–disable inputs cause
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MC14076B
MC14076B
r14525
MC14076B/D
14076B
MC14076BCP
MC14076BD
MC14076BDR2
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PDF
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Untitled
Abstract: No abstract text available
Text: MC14076B 4-Bit D-Type Register with Three-State Outputs The MC14076B 4−Bit Register consists of four D−type flip−flops operating synchronously from a common clock. OR gated output−disable inputs force the outputs into a high−impedance state for use in bus organized systems. OR gated data−disable inputs cause
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MC14076B
MC14076B
MC14076B/D
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PDF
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Untitled
Abstract: No abstract text available
Text: MC14076B 4-Bit D-Type Register with Three-State Outputs The MC14076B 4−Bit Register consists of four D−type flip−flops operating synchronously from a common clock. OR gated output−disable inputs force the outputs into a high−impedance state for use in bus organized systems. OR gated data−disable inputs cause
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MC14076B
PDIP-16
MC14076BCP
SOIC-16
MC14076B/D
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PDF
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MC14076B
Abstract: MC14076BCP MC14076BCPG MC14076BDG MC14076BDR2G
Text: MC14076B 4-Bit D-Type Register with Three-State Outputs The MC14076B 4−Bit Register consists of four D−type flip−flops operating synchronously from a common clock. OR gated output−disable inputs force the outputs into a high−impedance state for use in bus organized systems. OR gated data−disable inputs cause
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Original
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MC14076B
MC14076B
MC14076B/D
MC14076BCP
MC14076BCPG
MC14076BDG
MC14076BDR2G
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PDF
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Untitled
Abstract: No abstract text available
Text: MC14076B 4-Bit D-Type Register with Three-State Outputs The MC14076B 4−Bit Register consists of four D−type flip−flops operating synchronously from a common clock. OR gated output−disable inputs force the outputs into a high−impedance state for use in bus organized systems. OR gated data−disable inputs cause
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MC14076B
MC14076B
MC14076B/D
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BNC-2110
Abstract: 777643-01 PCI-6110 pxi-6115 184749-01 SH6868-EP 778241-01 6110 ni 6110 k 6115
Text: S Series Multifunction DAQ 12 or 16-Bit, 800 kS/s to 10 MS/s, 4 Analog Inputs • 2 or 4 analog inputs; dedicated A/D converter per channel • Analog and digital triggering • AC or DC coupling • 8 input ranges from ±200 mV to ±42 V • 2 analog outputs at 4 MS/s single
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16-Bit,
24-bit
68-pin
BNC-2110
777643-01
PCI-6110
pxi-6115
184749-01
SH6868-EP
778241-01
6110
ni 6110
k 6115
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PDF
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CB-68LPR
Abstract: BNC-2110 184749-02 SH68-68-EP SCXI-1125 labview programs for fir filter design by windows 777643-01 SCXI-1520 PCI-6110 mini pci convert pci
Text: S Series Multifunction DAQ 12 or 16-Bit, 1 to 10 MS/s, 4 Analog Inputs NI 6120, NI 6115, NI 6110, NI 6111 • 2 or 4 analog inputs; dedicated A/D converter per channel • 1 to 10 MS/s per channel maximum sample rate • Analog and digital triggering • AC or DC coupling
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16-Bit,
24-bit
2000/NT/XP
CB-68LPR
BNC-2110
184749-02
SH68-68-EP
SCXI-1125
labview programs for fir filter design by windows
777643-01
SCXI-1520
PCI-6110
mini pci convert pci
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PDF
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Untitled
Abstract: No abstract text available
Text: 74HC2G86; 74HCT2G86 Dual 2-input EXCLUSIVE-OR gate Rev. 4 — 14 March 2014 Product data sheet 1. General description The 74HC2G86; 74HCT2G86 is a dual 2-input EXCLUSIVE-OR gate. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages
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74HC2G86;
74HCT2G86
74HCT2G86
74HC2G86:
74HCT2G86:
JESD22-A114E
JESD22-A115-A
HCT2G86
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PDF
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74HC32
Abstract: hct32 NXP 74HC32D 74HC32D
Text: 74HC32; 74HCT32 Quad 2-input OR gate Rev. 5 — 4 September 2012 Product data sheet 1. General description The 74HC32; 74HCT32 is a quad 2-input OR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of
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74HC32;
74HCT32
74HCT32
74HC32:
74HCT32:
JESD22-A114F
JESD22-A115-A
HCT32
74HC32
hct32
NXP 74HC32D
74HC32D
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PDF
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Untitled
Abstract: No abstract text available
Text: 74HC32; 74HCT32 Quad 2-input OR gate Rev. 5 — 4 September 2012 Product data sheet 1. General description The 74HC32; 74HCT32 is a quad 2-input OR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of
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74HC32;
74HCT32
74HCT32
74HC32:
74HCT32:
JESD22-A114F
JESD22-A115-A
HCT32
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PDF
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Untitled
Abstract: No abstract text available
Text: 74HC2G32; 74HCT2G32 Dual 2-input OR gate Rev. 4 — 27 September 2013 Product data sheet 1. General description The 74HC2G32; 74HCT2G32 is a dual 2-input OR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of
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Original
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74HC2G32;
74HCT2G32
74HCT2G32
74HC2G32:
74HCT2G32:
JESD22-A114E
JESD22-A115-A
HCT2G32
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PDF
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CY2DP314
Abstract: CY2DP314OI CY2DP314OIT CY2DP314OXI CY2DP314OXIT P314
Text: CY2DP314 1:4 Differential Clock/Data Fanout Buffer Features Functional Description • Four ECL/PECL differential outputs • One ECL/PECL differential or single-ended inputs CLKA • One HSTL differential or single-ended inputs (CLKB) • Hot-swappable/-insertable
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CY2DP314
CY2DP314
CY2DP314OI
CY2DP314OIT
CY2DP314OXI
CY2DP314OXIT
P314
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PDF
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p314v
Abstract: No abstract text available
Text: FastEdge Series CY2DP314 1 of 2:4 Differential Clock/Data Fanout Buffer Features Functional Description • Four ECL/PECL differential outputs • One ECL/PECL differential or single-ended inputs CLKA • One HSTL differential or single-ended inputs (CLKB)
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CY2DP314
20-pin
CY2DP314
p314v
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PDF
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CY2DP314
Abstract: CY2DP314OI CY2DP314OIT CY2DP314OXI CY2DP314OXIT P314 13VAC
Text: CY2DP314 1 of 2:4 Differential Clock/Data Fanout Buffer Features Functional Description • Four ECL/PECL differential outputs • One ECL/PECL differential or single-ended inputs CLKA • One HSTL differential or single-ended inputs (CLKB) • Hot-swappable/-insertable
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CY2DP314
CY2DP314
CY2DP314OI
CY2DP314OIT
CY2DP314OXI
CY2DP314OXIT
P314
13VAC
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PDF
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PCI-6111E
Abstract: TBX-68 SH68-68-EP CB-68LP national instruments 68M-50F pin SH6868-EP PCI-611E
Text: PCI-6110E, PCI-6111E E Series Multifunction I/O – 5 MS/s, 12-Bit, Simultaneous-Sampling, 2 or 4 Analog Inputs PCI-6110E, PCI-6111E Available Q1 1998 Analog Input 4 differential inputs PCI-6110E 2 differential inputs (PCI-6111E) 12-bit resolution 5 MS/s simultaneous sampling rate
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PCI-6110E,
PCI-6111E
12-Bit,
PCI-6111E
PCI-6110E)
PCI-6111E)
12-bit
16-bit
24-bit
TBX-68
SH68-68-EP
CB-68LP
national instruments 68M-50F pin
SH6868-EP
PCI-611E
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PDF
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Untitled
Abstract: No abstract text available
Text: C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC4071BP/BF/BFNJC4072BP/BF TC4075BP/BF TC4071B QUAD 2 INPUT OR GATE TC4072B DUAL 4 INPUT OR GATE TC4075B TRIPLE 3 INPUT OR GATE TC4071B, TC4075BP / BF and TC4072BP / BF are positive logic OR gates w ith tw o inputs, three inputs and fo ur inputs
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OCR Scan
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TC4071BP/BF/BFNJC4072BP/BF
TC4075BP/BF
TC4071B
TC4072B
TC4075B
TC4071B,
TC4075BP
TC4072BP
TC4071B
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PDF
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hd1407
Abstract: VEI 005 14076b
Text: HD14076B 4 - b i t D -ty p e Register The HD14076B 4-bit Register consists of four D-type flip-flops operating synchronously from a common clock. OR gated outputdisable inputs force the outputs into a high-impedance state for use in bus organized systems. OR gated data-disable inputs cause the Q
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OCR Scan
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HD14076B
HD14076B
14076B
VW-10V
hd1407
VEI 005
14076b
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PDF
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HEF40* nand
Abstract: No abstract text available
Text: HEF4086B 4-WIDE 2-INPUT AND-OR-INVERT GATE The HEF4086B is a 4-wide 2-input AND-OR-invert AOI gate with two additional inputs Os and ig) which can be used as either expander_or inhibit inputs by connecting them to any standard LOCMOS output. A HIGH on Ig or a LOW on Tg forces the output (0) LOW independent of the other eight
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OCR Scan
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HEF4086B
HEF4086B
7Z73702
HEF4086BPIN)
14-lead
HEF4Q86B
HEF40* nand
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PDF
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HEF4086B
Abstract: HEF4086BD HEF4086BP HEF4086BT CL555
Text: HEF4086B gates 4-WIDE 2-INPUT AND-OR-INVERT GATE The HEF4086B is a 4-wide 2-input AND-OR-invert AOI gate with two additional inputs (Ig and Fg) which can be used as either expanderor inhibit inputs by connecting them to any standard LOCMOS output. A HIGH on Ig or a LOW on Ig forces the output (O) LOW independent of the other eight
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OCR Scan
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HEF4086B
7Z73702
7Z73701
HEF4086BP
7Z85104
HEF4086BD
HEF4086BT
CL555
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PDF
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Untitled
Abstract: No abstract text available
Text: 4071B 4072B 4075B INTERNATIONAL, INC CMOS OR GATES 4071B - Quad 2-Input OR 4072B - Dual 4-Input OR 4075B - Triple 3-Input OR CONNECTION DIAGRAMS all packages FEATURES 4 ♦ ♦ Buffered Outputs Diode Protection on all Inputs Fully "B"-Series Compatible TRUTH TABLE
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OCR Scan
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4071B
4072B
4075B
4071B
4072B
4075B
4000B
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PDF
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54164
Abstract: No abstract text available
Text: SN54164, SN54LS164. SN74164, SN74LS164 8 BIT PARALLEL OUT SERIAL SHIFT REGISTERS M ARCH 1974 - REVISED M AR CH 1988 • Gated Serial Inputs SN 54164, SN 54LS164 . . . J OR W PACKAG E SN 74164 . . . N PACKAG E S N 7 4 L S 1 6 4 . . . D OR N P A C K A G E • Fully Buffered Clock and Serial Inputs
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OCR Scan
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SN54164,
SN54LS164.
SN74164,
SN74LS164
54LS164
LS164
54164
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PDF
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SRQ10
Abstract: No abstract text available
Text: 74ACT11898 10-BIT PARALLEL-OUT SERIAL SHIFT REGISTER D3644. OCTOBER 1990-R EV ISE D APRIL1993 DW OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible AND-Gated (Enable/Disable) Serial Inputs Fully Buffered Clock and Serial Inputs 1 2 3 4 5 6 7 qf [ 8
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OCR Scan
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74ACT11898
10-BIT
D3644.
1990-R
APRIL1993
500-mA
300-mil
SRQ10
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PDF
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Untitled
Abstract: No abstract text available
Text: 74LCX32 LOW VOLTAGE CMOS QUAD 2-INPUT OR GATE 5V TOLERANT INPUTS . 5VTOLERANT INPUTS • HIGHSPEED: tpD = 5.5 ns MAX. at Vcc = 3 V ■ POWER-DOWN PROTECTION ON INPUTS AND OUTPUTS . SYMMETRICAL OUTPUT IMPEDANCE: |Io h | = Io l = 2 4 m A (M IN ) . PCI BUS LEVELS GUARANTEED AT 24mA
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OCR Scan
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74LCX32
74LCX32M
74LCX32T
EXCEEDS500mA
LCX32
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PDF
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