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    36V18 Search Results

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    CYD36S36V18-167BGXI Rochester Electronics 1MX36 DUAL-PORT SRAM, 4ns, PBGA484, 27 X 27 MM, 2.33 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-484 Visit Rochester Electronics Buy
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    36V18 Price and Stock

    Delta Electronics Inc LNE-36V185WAAA

    LED DRIVER CC/CV AC/DC 36V 5.2A
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    Rochester Electronics LLC CYD02S36V18-167BBC

    IC SRAM 2MBIT PAR 167MHZ 256FBGA
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    Infineon Technologies AG CYD02S36V18-167BBC

    IC SRAM 2MBIT PAR 167MHZ 256FBGA
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    Rochester Electronics LLC CYD02S36V18-200BBC

    IC SRAM 2MBIT PARALLEL 256FBGA
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    Infineon Technologies AG CYD36S36V18-200BBXC

    IC SRAM 36MBIT PARALLEL 256FBGA
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    36V18 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text:  XC95576 In-System Programmable CPLD June 1, 1996 Version 1.0 Advance Product Specification Features Description • • • • • The XC95576 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of thirtytwo 36V18 Function Blocks, providing 12,800 usable gates


    Original     		PDF XC95576 36V18 304-pin

    36V18

    Abstract: No abstract text available
    Text:  XC95432 In-System Programmable CPLD June 1, 1996 Version 1.0 Advance Product Specification Features Description • • • • • The XC95432 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of twentyfour 36V18 Function Blocks, providing 9,600 usable gates


    Original     		PDF XC95432 36V18 304-pin

    XC9572

    Abstract: XC9572-10PC44C xc9572-15PQ100 15PC44I xc9572 data sheet XC9572-7PC44C PC44 PC84 xc9572-10pq100c XC9572-15PC84C
    Text: XC9572 In-System Programmable CPLD R DS065 v4.2 April 15, 2005 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz • • • 72 macrocells with 1,600 usable gates Up to 72 user I/O pins 5V in-system programmable


    Original     		PDF XC9572 DS065 36V18 XC9572-10PC44C xc9572-15PQ100 15PC44I xc9572 data sheet XC9572-7PC44C PC44 PC84 xc9572-10pq100c XC9572-15PC84C

    Untitled

    Abstract: No abstract text available
    Text: – PRODUCT OBSOLETE / UNDER OBSOLESCENCE – k XC9500 In-System Programmable CPLD Family R DS063 v6.0 May 17, 2013 Product Specification Features - Advanced CMOS 5V FastFLASH technology • - Supports parallel programming of multiple XC9500 devices High-performance


    Original     		PDF XC9500 DS063 XC9500 36V18 produ2/10/1999 XC95288. 352-pin XC95216. XCN07010 XCN11010

    PLCC-48 footprint

    Abstract: XC95108 XC95144 XC95216 XC95288 XC9536 XC9572 XC9500 XC9500 pinout
    Text: XC9500 In-System Programmable CPLD Family R December 14, 1998 Version 3.0 1* Features Family Overview • The XC9500 CPLD family provides advanced in-system programming and test capabilities for high performance, general purpose logic integration. All devices are in-system


    Original     		PDF XC9500 PLCC-48 footprint XC95108 XC95144 XC95216 XC95288 XC9536 XC9572 XC9500 pinout

    XC9500

    Abstract: XC95108 GSR 10,8
    Text: 1 XC95108 In-System Programmable CPLD  December 4, 1998 Version 3.0 1 1* Product Specification Features Power Management • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz • • • 108 macrocells with 2400 usable gates Up to 108 user I/O pins


    Original     		PDF XC95108 36V18 84-Pin 100-Pin 160-Pin XC95108 PQ100 TQ100 PQ160 XC9500 GSR 10,8

    XC95108

    Abstract: XC95108-10PQ160C xc95108-10pqg100i XC95108-20PQG160I TQG100 XC95108-15PC84C PGC84 XC95108-20PQ100I
    Text: – PRODUCT OBSOLETE / UNDER OBSOLESCENCE – XC95108 In-System Programmable CPLD R DS066 v5.0 May 17, 2013 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz • • • 108 macrocells with 2,400 usable gates


    Original     		PDF XC95108 DS066 36V18 PQ160 XCN11010 XC95108-10PQ160C xc95108-10pqg100i XC95108-20PQG160I TQG100 XC95108-15PC84C PGC84 XC95108-20PQ100I

    XC9572

    Abstract: XC9572 Family PC84 PQ100 XC9500 xc9572 tq100
    Text: 1 XC9572 In-System Programmable CPLD  December 4, 1998 Version 3.0 1 1* Product Specification Features Power Management • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz • • • 72 macrocells with 1,600 usable gates Up to 72 user I/O pins


    Original     		PDF XC9572 36V18 44-Pin 84-Pin 100-Pin XC9572 PQ100 TQ100 XC9572 Family PC84 PQ100 XC9500 xc9572 tq100

    XC4010-5PG191M

    Abstract: XC4005-5PG156M PA44-48U adapter datasheet pa44-48u SDP72 xilinx 1736a 5962-9230503MXC XC4010-5CB196B SDP-UNIV-44 XC4010-5CB196M
    Text: XCELL THE QUARTERLY Issue 19 Fourth Quarter 1995 JOURNAL FOR XILINX PROGRAMMABLE LOGIC USERS GENERALFEATURES R The Programmable Logic CompanySM Inside This Issue: GENERAL Fawcett: 100,000+ Gates . 2 Guest Editorial . 3


    Original     		PDF

    471 E25

    Abstract: PQ160 XC9500 XC95216
    Text: XC95216 In-System Programmable CPLD  October 28, 1997 Version 2.0 3* Product Specification Features Power Management • • • • • Power dissipation can be reduced in the XC95216 by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize


    Original     		PDF XC95216 36V18 PQ160 160-Pin HQ208 208-Pin BG352 471 E25 XC9500

    XC9572

    Abstract: xc9572 data sheet XC9572-15PC84C XC9572-7PCG84C XC9572-15PQG100I XC9572-10PQ100C XC9572-7TQG100C XC9572-15PCG44C XC9572-10PQ100I XC9572-10PC44I
    Text: XC9572 In-System Programmable CPLD R DS065 v4.3 April 3, 2006 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz • • • 72 macrocells with 1,600 usable gates Up to 72 user I/O pins 5V in-system programmable


    Original     		PDF XC9572 DS065 36V18 xc9572 data sheet XC9572-15PC84C XC9572-7PCG84C XC9572-15PQG100I XC9572-10PQ100C XC9572-7TQG100C XC9572-15PCG44C XC9572-10PQ100I XC9572-10PC44I

    471 E25

    Abstract: XC95216 Family 134-174 PQ160 XC9500 XC95216
    Text: 1 XC95216 In-System Programmable CPLD  August 21, 2001 Version 3.1 1 0* Product Specification Features Power Management • • 10 ns pin-to-pin logic delays on all pins fCNT to 111 MHz • • • 216 macrocells with 4800 usable gates Up to 166 user I/O pins


    Original     		PDF XC95216 36V18 PQ160 160-Pin HQ208 208-Pin BG352 352-Pin XC95216 PQ160 471 E25 XC95216 Family 134-174 XC9500

    XC95216-20PQG160I

    Abstract: XC95216-15PQ160I 471 E25 XC95216 Family XC95216-10PQ160C XC95216-10PQ160I XC95216-15PQG160C XC95216-15PQG160I XC95216-10PQG160I XC9500
    Text: XC95216 In-System Programmable CPLD R 5 Note: The 352-pin BGA packages are being discontinued for XC95216 devices. You cannot order these packages after May 14, 2008. Xilinx recommends replacing XC95216 in 352-pin BGA packages with XC95288 devices in 352-pin BGA packages in all designs as soon as possible. Recommended replacements are pin compatible, but


    Original     		PDF XC95216 352-pin XC95288 XCN07010 352-pin XC95216-20PQG160I XC95216-15PQ160I 471 E25 XC95216 Family XC95216-10PQ160C XC95216-10PQ160I XC95216-15PQG160C XC95216-15PQG160I XC95216-10PQG160I XC9500

    XC9536

    Abstract: XC9536-6 XC9536-7 XC9500 XC9536-10 XC9536-15 XC9536-5 xc9536 44 pin vqfp
    Text: 9 1 XC9536 In-System Programmable CPLD  December 4, 1998 Version 5.0 1 1* Product Specification Features Power Management • • 5 ns pin-to-pin logic delays on all pins fCNT to 100 MHz • • • 36 macrocells with 800 usable gates Up to 34 user I/O pins


    Original     		PDF XC9536 36V18 XC9536 XC9536-6 XC9536-7 XC9500 XC9536-10 XC9536-15 XC9536-5 xc9536 44 pin vqfp

    XC95144

    Abstract: XC95144-10PQG100I XC95144-10PQG160C xc9514415pqg160i Plastic Quad Flat Pack PQFP XC95144-10TQG100I xc95144-15pqg100i XC95144-7PQG160C XC95144-15PQG160C XC95144-15pqg160i
    Text: XC95144 In-System Programmable CPLD R DS067 v5.6 April 3, 2006 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 111 MHz • • • 144 macrocells with 3,200 usable gates Up to 133 user I/O pins 5V in-system programmable


    Original     		PDF XC95144 DS067 36V18 PQ160 XC95144-10PQG100I XC95144-10PQG160C xc9514415pqg160i Plastic Quad Flat Pack PQFP XC95144-10TQG100I xc95144-15pqg100i XC95144-7PQG160C XC95144-15PQG160C XC95144-15pqg160i

    XC95288

    Abstract: BG352 HQ208 XC9500 n439
    Text: XC95288 In-System Programmable CPLD R DS069 v4.1 August 21, 2003 5 Product Specification Features Description • • 15 ns pin-to-pin logic delays on all pins fCNT to 95 MHz • • • 288 macrocells with 6,400 usable gates Up to 166 user I/O pins 5V in-system programmable


    Original     		PDF XC95288 DS069 36V18 BG352 352-ball XC95288-20HQ208I HQ208 208-pin XC95288-20BG352I BG352 HQ208 XC9500 n439

    XC95144

    Abstract: DS06 HW130 XC9500 XC95108 XC95216 XC95288 XC9536 XC9572 xc95144 pinout
    Text: k XC9500 In-System Programmable CPLD Family R DS063 v5.1 September 22, 2003 Product Specification Features - Advanced CMOS 5V Fast FLASH technology • - Supports parallel programming of multiple XC9500 devices • High-performance - 5 ns pin-to-pin logic delays on all pins


    Original     		PDF XC9500 DS063 XC9500 36V18 Func500 XC95288. XC95144 DS06 HW130 XC95108 XC95216 XC95288 XC9536 XC9572 xc95144 pinout

    xc9572-44 pin

    Abstract: xc9536 44 pin vqfp XC9536 36V18 TQ100 VQ44 XC9500 XC9536-15VQ44Q XC9572 XC9572-15TQ100Q
    Text: k XC9500 In-System Programmable CPLD Automotive IQ Family R DS120-1 v1.2 October 18, 2004 Features • System frequency up to 55 MHz • Guaranteed to meet full electrical specifications over TA = –40 to +125°C • 5V in-system programmable - Endurance of 10,000 program/erase cycles


    Original     		PDF XC9500 DS120-1 36V18 XC9536-15VQ44Q 44-pin XC9572-15TQ100Q TQ100 100-pin xc9572-44 pin xc9536 44 pin vqfp XC9536 TQ100 VQ44 XC9536-15VQ44Q XC9572 XC9572-15TQ100Q

    XC95144 PQ100

    Abstract: XC95144 XC95144-15TQG100C XC95144-15TQG100I XC95144-10PQ100I PQ100 PQ160 TQ100 XC9500 XC95144-15PQ100
    Text: XC95144 In-System Programmable CPLD R DS067 v5.7 May 28, 2009 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 111 MHz • • • 144 macrocells with 3,200 usable gates Up to 133 user I/O pins 5V in-system programmable


    Original     		PDF XC95144 DS067 36V18 XC95144 PQ100 XC95144-15TQG100C XC95144-15TQG100I XC95144-10PQ100I PQ100 PQ160 TQ100 XC9500 XC95144-15PQ100

    471 E25

    Abstract: xc95288 XC95288-15HQ208I AD9318 A23 780-4 BG352 HQ208 XC9500 h3144 n439
    Text: XC95288 In-System Programmable CPLD R DS069 v4.3 April 3, 2006 5 Product Specification Features Description • • 15 ns pin-to-pin logic delays on all pins fCNT to 95 MHz • • • 288 macrocells with 6,400 usable gates Up to 166 user I/O pins 5V in-system programmable


    Original     		PDF XC95288 DS069 36V18 471 E25 XC95288-15HQ208I AD9318 A23 780-4 BG352 HQ208 XC9500 h3144 n439

    Untitled

    Abstract: No abstract text available
    Text: KXILINX XC95432 In-System Programmable CPLD Jun e 1, 1996 V ersion 1.0 Advance Product Specification Features Description • • • • • The XC95432 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of twentyfour 36V18 Function Blocks, providing 9,600 usable gates


    OCR Scan     		PDF XC95432 36V18 304-pin

    Untitled

    Abstract: No abstract text available
    Text: tlX IU N X XC95432 In-System Programmable CPLD January, 1997 Version 1.0 Advanced Product Specification Features Description • • • • • The XC95432 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of twentyfour 36V18 Function Blocks, providing 9,600 usable gates


    OCR Scan     		PDF XC95432 36V18 XC9500 432-pin

    Untitled

    Abstract: No abstract text available
    Text: flX IU N X XC9536 In-System Programmable CPLD October 29, 1997 Version 2.0 Product Specification Features Power Management 5 ns pin-to-pin logic delays on all pins • • • • • • • • • • • • • fcNT to MHz 36 macrocells with 800 usable gates


    OCR Scan     		PDF XC9536 36V18 44-Pin XC9536

    XC95288

    Abstract: No abstract text available
    Text: flXIUNX XC95288 In-System Programmable CPLD December 4, 1998 Version 3.0 Product Specification Features Power Management • • 15 ns pin-to-pin logic delays on all pins fcN T 95 MHz • • • 288 macrocells with 6,400 usable gates Up to 192 user I/O pins


    OCR Scan     		PDF XC95288 36V18 HQ208 208-Pin BG352 352-Pin