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    R5C847

    Abstract: IT8512 RC415M ITE8512 ite 8512 embedded controller diagram it8512 quanta ATI SB600 RC415MD quanta computer
    Text: 5 4 AK24 3 CPU 1 01 CPU Thermal Sensor PAGE 3 Yonah/Celeron BlOCK DIAGRAM 2 u-FCPGA 479PIN NB Thermal Sensor PAGE 3,4 PAGE 5 D D FSB Battery 533 MHZ Memory single channel DC/DC & Charge PAGE 35 DC In CRT DDC2B SO-DIMM NORMAL DDR II CHANNEL 533 MHZ PAGE 11


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    PDF 479PIN RC415MD 15-Pin 33MHZ R5C847 66/100MHz SB600 Page13: Page24: R5C847 IT8512 RC415M ITE8512 ite 8512 embedded controller diagram it8512 quanta ATI SB600 RC415MD quanta computer

    555 timer

    Abstract: application note ic 555 IC 555 timer bistable ic 555 block diagram ic 555 timer IC 555 pin DIAGRAM 555 timer project signetics 555 pin diagram of ic 555 Ic analog 555
    Text: Application Note AN2286 Simulating a 555 Timer with PSoC Author: Dave Van Ess Associated Project: Yes Associated Part Family: Any PSoC Designer Version: 4.2 Abstract The PSoC Mixed-Signal Array is a versatile system-on-chip that facilitates complete system design. But can


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    PDF AN2286 555 timer application note ic 555 IC 555 timer bistable ic 555 block diagram ic 555 timer IC 555 pin DIAGRAM 555 timer project signetics 555 pin diagram of ic 555 Ic analog 555

    MA6116

    Abstract: KBC-NS87551L C37B 31KT2MB0018 ad30 c635 100v 10p quanta ACAD12 2522A diode dd 402 109 bn2 scan 100 27p
    Text: 5 4 3 2 PCB Rev: C D Sch ver : 20040514-1 KT2 BLOCK DIAGRAM 31KT2MB0018 PCB STACK UP LAYER 1 : TOP KT2 APJ D PENTIUM-M / Montara-GM / ICH4-M LAYER 2 : GND LAYER 3 : IN1 CPU PENTIUM-M CPU THERMAL SENSOR GMT-781 LAYER 4 : IN2 14.318MHz SYSTEM POWER(1.2V/1.05V/1.25V)


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    PDF GMT-781 31KT2MB0018 318MHz CY28346/ ICS950810 4X100MHZ MAX1907 MAX1999 DTC144EUA 2N7002E MA6116 KBC-NS87551L C37B 31KT2MB0018 ad30 c635 100v 10p quanta ACAD12 2522A diode dd 402 109 bn2 scan 100 27p

    Bd3 semiconductor

    Abstract: TMS320C549 DC549 BA13 SFM140L2SDLC 20-PIN BA21 BA22 SL14 BDR-1
    Text: 8 7 6 5 4 3 2 1 REVISIONS NOTES, UNLESS OTHERWISE SPECIFIED: REV 1. VCC IS APPLIED TO PIN 8 OF ALL 8-PIN IC'S, PIN 14 OF ALL 14-PIN IC'S, PIN 16 OF ALL 16-PIN IC'S, PIN 20 OF ALL 20-PIN IC'S, ETC. DESCRIPTION DATE APPROVED * 2. GROUND IS APPLIED TO PIN 4 OF ALL 8-PIN IC'S,


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    PDF 14-PIN 16-PIN 20-PIN Bd3 semiconductor TMS320C549 DC549 BA13 SFM140L2SDLC BA21 BA22 SL14 BDR-1

    MA6116

    Abstract: t30 55 TMS 3617 31KT2MB0026 capacitor 100u 63V cpu c644 100v 27p PC97 quanta PCI 1520 quanta computer
    Text: 5 4 3 2 PCB Rev: C D Sch ver : 20040514-1 KT2 BLOCK DIAGRAM 31KT2MB0026 PCB STACK UP LAYER 1 : TOP KT2 FF D PENTIUM-M / Montara-GM / ICH4-M LAYER 2 : GND LAYER 3 : IN1 CPU PENTIUM-M CPU THERMAL SENSOR GMT-781 LAYER 4 : IN2 14.318MHz SYSTEM POWER(1.2V/1.05V/1.25V)


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    PDF GMT-781 31KT2MB0026 318MHz CY28346/ ICS950810 4X100MHZ MAX1907 MAX1999 DTC144EUA 2N7002E MA6116 t30 55 TMS 3617 31KT2MB0026 capacitor 100u 63V cpu c644 100v 27p PC97 quanta PCI 1520 quanta computer

    HDR20X2

    Abstract: 5R14 43A16 CTL036 CONN10X2 4a20 27A14 MEMDATA23 PD153 20A7
    Text: 8 7 6 5 4 3 2 1 VUSB VUSB_FP3 VIN V4P6 2 J3 VIN 1 U22 TPS79601 JUMPER5STAR D 2 3 2VIN VIN 1 JP9 JP10 1 3 +5.0V DC IN 4 5 4.66V VIN_CONN VOUT4 1EN FB2 D FB5 GND 3 TABGND 6 2 FERRITE_BEAD C16 15 PF R22 84.5K 1% PJ-102A 1 2 3 4 5 6 7 8 9 10 FROM MOTHER BOARD


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    PDF TPS79601 PJ-102A HDR10 51GND51 67GND67 75GND75 86GND86 88GND88 27IO27 HDR20X2 5R14 43A16 CTL036 CONN10X2 4a20 27A14 MEMDATA23 PD153 20A7

    SP8K10SFD5_ROHM

    Abstract: LPC47N249 inventec C5686 D5073 23D36 ddr2 C5706 c5690 SP8K10
    Text: KNOCKHILL20 MP BUILD EE DATE POWER DATE DRAWER DESIGN CHECK RESPONSIBLE DATE CHANGE NO. REV SIZE = 3 FILE NAME : XXXX-XXXXXX-XX P/N XXXXXXXXXXXX INVENTEC TITLE VER : Knockhill 20 SIZE CODE A3 CS SHEET DOC. NUMBER REV Model_No 1 OF A03 61 TABLE OF CONTENTS


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    PDF KNOCKHILL20 CN3000 AF312K AF306K SW3000 CN3001 A106T SW3001 A106T FIX4023 SP8K10SFD5_ROHM LPC47N249 inventec C5686 D5073 23D36 ddr2 C5706 c5690 SP8K10

    BAT54

    Abstract: RC410M BAT54C3 27b4 INVENTEC SP8K10SFD5_ROHM ATI SB450 KNOCKHILL 10 12ah3 P19E-6
    Text: San Antonio 10E PreMP BUILD EE DATE POWER DATE DRAWER DESIGN CHECK RESPONSIBLE DATE CHANGE NO. REV SIZE = 3 FILE NAME : XXXX-XXXXXX-XX P/N XXXXXXXXXXXX INVENTEC TITLE VER : Knockhill 10A SIZE CODE A3 DOC. NUMBER REV X01 CS SHEET 1 OF 50 TABLE OF CONTENTS PAGE


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    PDF 6-Aug-2005 D2000 CN2000 SW2001 A106T SW2000 A106T FIX14 FIX10 FIX11 BAT54 RC410M BAT54C3 27b4 INVENTEC SP8K10SFD5_ROHM ATI SB450 KNOCKHILL 10 12ah3 P19E-6

    ITE 8512

    Abstract: g545b2 R5C847 ite 8512 embedded controller IT8512 ATI RC415MD GMT781 ITE8512 RC415MD ATI sb600
    Text: 5 4 AK23 3 CPU 1 01 CPU Thermal Sensor PAGE 3 Yonah/Celeron BlOCK DIAGRAM 2 u-FCPGA 479PIN NB Thermal Sensor PAGE 3,4 PAGE 5 D D FSB Battery 533 MHZ Memory single channel DC/DC & Charge PAGE 35 DC In CRT DDC2B SO-DIMM NORMAL DDR II CHANNEL 533 MHZ PAGE 11


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    PDF 479PIN RC415MD 15-Pin 33MHZ R5C847 66/100MHz SB600 Page26 Page27 ITE 8512 g545b2 R5C847 ite 8512 embedded controller IT8512 ATI RC415MD GMT781 ITE8512 RC415MD ATI sb600

    Untitled

    Abstract: No abstract text available
    Text: First-In First-Out FIFO 64x4 64x5 Memory 15 MHz (Cascadable) C67L401D C67L402D Ordering Inform ation Features/ Benefits • High-speed 15-MHz shift-in/shift-oul rates • Low power consumption PART NUMBER PKG TEMP DESCRIPTION • Choice of 4-bit or 5-bit data width


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    PDF 15-MHz C67L401 C67L402D C67L401D C67L402D C67L401D C67L402D) C67L401D/2D 77T/777T ord63isem

    Untitled

    Abstract: No abstract text available
    Text: HD6305X1 ,HD63A05X1 ,HD63B05X1— HD6305X2,HD63A05X2,HD63B05X2 C M O S M C U M icrocom puter Unit The HD6305XI and the HD6305X2 are memory expanda­ ble versions of the HD6305X0, which is CMOS 8-bit single chip microcomputer. A CPU, a clock generator, a 128-byte RAM ,


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    PDF HD6305X1 HD63A05X1 HD63B05X1â HD6305X2 HD63A05X2 HD63B05X2 HD6305XI HD6305X0, 128-byte

    74LVC86

    Abstract: 74LV86 74LVC86D 74LVC86DB 74LVC86PW
    Text: Philips Semiconductors Product Specification Quad 2-input EXCLUSIVE-OR gate FEATURES • • • • • 74LVC86 QUICK REFERENCE DATA GNP = 0 V; T ^ = 25°C; t, = t, < 2.5 ns W ide s u p p ly vo lta g e range o f 1.2 V to 3.6 V In accorda nce w ith JEDEC sta nd ard no. 8-1 A.


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    PDF 74LVC86 74LVC86 74LV86 711002b 74LVC86D 74LVC86DB 74LVC86PW

    Untitled

    Abstract: No abstract text available
    Text: 74S280 Signetics Parity Generator/Checker 9-Bit Odd/Even Parity Generator/Checker Product Specification Logic Products FEATURES • Buffered inputs — one normalized load • Word-length easily expanded by cascading • Similar pin configuration to '180 for easy system up-grading


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    PDF 74S280 N74S280N 500ns 500ns

    74LV08

    Abstract: 74LV08D 74LV08DB 74LV08N 74LV08PW
    Text: Philips Semiconductors Product Specification Quad 2-input AND gate FEATURES • • • • • • 74LV08 QUICK REFERENCE DATA GND = 0 V ; T wrb = 25°C; t, = t, < 2.5 ns Optimized for Low Voltage applications: 1.0 to 3.6 V Accepts TTL input levels between Vcc = 2.7 V and


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    PDF 74LV08 74HC/HCT08. 711D6Sb 007520b 74LV08D 74LV08DB 74LV08N 74LV08PW

    DAC 0-10v

    Abstract: NE5018 laf 001
    Text: Philips Sem iconductors Linear Products Product specification 8-Bit jip-compatible D/A converter NE/SE5018/5019 DESCRIPTION PIN CONFIGURATIONS The NE/SE5018/19 is a complete 8 -bit cligilal-to-analog converter subsystem on one monolithic chip. The data inputs have input


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    PDF NE/SE5018/5019 NE/SE5018/19 711002b 711052b 711DA2b DAC 0-10v NE5018 laf 001

    74LVC74D DC Characteristics

    Abstract: 74LVC74 74LVC74D 74LVC74DB 74LVC74PW Dual D-type flip-flop
    Text: Philips Semiconductors Product Specification Dual D-type flip-flop with set and reset; positive-edge trigger FEATURES 74LVC74 QUICK REFERENCE DATA GND = 0 V; T ^ = 25°C; t, = t, =2.5 ns • • • • • • Wide supply voltage range of 1.2 V to 3.6 V In accordance with JEDEC


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    PDF 74LVC74 74LVC74 D100512 74LVC74D DC Characteristics 74LVC74D 74LVC74DB 74LVC74PW Dual D-type flip-flop

    CNY 13-3

    Abstract: F-tmb 74HC/HCT132 74lv1320 cny 76 VH 73 74LV132 74LV132D 74LV132DB 74LV132N
    Text: Philips Semiconductors Preliminary Specification Quad 2-input NAND Schmitt-trigger eFEATURES 74LV132 QUICK REFERENCE DATA • Optimized for Low Voltage applications: 1.0 to 3.6 V • Accepts TTL input levels between Vcc = 2.7 V and Vcc = 3.6 V • Typical V0LP output ground


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    PDF 74LV132 74LV132 74HC/HCT132. 711002b CNY 13-3 F-tmb 74HC/HCT132 74lv1320 cny 76 VH 73 74LV132D 74LV132DB 74LV132N

    1CL232

    Abstract: ICL232CPE ICL232 circuit diagram for simple IR transmitter receiver s431
    Text: ICL232 HARRIS SEMI CONDUCTOR + 5 Volt Powered Dual RS-232 T ransmitter/Receiver GENERAL DESCRIPTION FEATURES The ICL232 is a dual RS-232 transmitter/receiver inter­ face circuit that meets all EIA RS-232C specifications. It requires a single + 5V power supply, and features two on­


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    PDF ICL232 RS-232 RS-232C ICL232 5-TT22 1CL232 ICL232CPE circuit diagram for simple IR transmitter receiver s431

    74157 pin diagram

    Abstract: ttl 74157 pin diagram multiplexer 74157 TTL 74158 74157 74158 pin diagram of 74157 74157 pin configuration N74LS157N LS157
    Text: Sjgnetìcs 74157, 74158, LS157, LS158, S157, S158 Data Selectors/Multiplexers '157 Quad 2-Input Data Selector/Multiplexer Non-lnverted '158 Quad 2-Input Data Selector/Multiplexer (Inverted) Product Specification Logic Products DESCRIPTION The '157 is a quad 2-input multiplexer


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    PDF LS157, LS158, 74157 pin diagram ttl 74157 pin diagram multiplexer 74157 TTL 74158 74157 74158 pin diagram of 74157 74157 pin configuration N74LS157N LS157

    74LVC74

    Abstract: 74LVC74D 74LVC74DB SSOP14 74LVC74D DC Characteristics 74LVC74 Philips
    Text: NAPC/PHILIPS SEMICON] b3E T> • bbS3ci24 DOflBflfl1} bSS « S I C S Philips Semiconductors Objective Specification Dual D-type flip-flop with set and reset; positive-edge trigger FEATURES • • • • • • Wide supply voltage range of 1.2 V to 3.6 V


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    PDF 74LVC74 74LVC74D 74LVC74DB SSOP14 74LVC74D DC Characteristics 74LVC74 Philips

    74ls112 pin diagram

    Abstract: 74ls112 pin configuration 74LS112 N74S112D 74ls112 function table
    Text: 7 4 LS1 1 2 , S 1 1 2 Flip-Flops S ig n e t ic s Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION The '112 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, Clock, Set and_Reset inputs. The Set So and Reset (R d) inputs, when LOW,


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    PDF 1N916, 1N3064, 500ns 500ns 74ls112 pin diagram 74ls112 pin configuration 74LS112 N74S112D 74ls112 function table

    17AW

    Abstract: No abstract text available
    Text: HIP6005B Semiconductor Data Sheet November 1998 Buck Pulse-Width Modulator PWM Controller and Output Voltage Monitor T he H IP 60 05 B pro vid es com p le te con tro l and pro te ction for a D C -D C c o n ve rte r op tim ize d for high -perform a nce File Number 4568.1


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    PDF HIP6005B 6005B 1-800-4-HARRIS 17AW