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    Teledyne e2v PALC22V10-30TMB

    PROG. LOGIC DEVICE, UV ERASABLE, 22-INPU - Rail/Tube (Alt: PALC22V10-30TMB)
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    Teledyne e2v PALC16R6-30TMB

    PROG. LOGIC DEVICE, UV ERASABLE, 16-INPU - Rail/Tube (Alt: PALC16R6-30TMB)
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    Teledyne e2v WS27C256L-30TMB

    PROM, UV ERASABLE, 32K X 8, 300 NS ACCES - Rail/Tube (Alt: WS27C256L-30TMB)
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    Teledyne e2v PALC16R8-30TMB

    PROG. LOGIC DEVICE, UV ERASABLE, 16-INPU - Rail/Tube (Alt: PALC16R8-30TMB)
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    Coilcraft Inc 0805HS-030TMBC

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    Bristol Electronics 0805HS-030TMBC 2,000
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    0805HS-030TMBC 2,700
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    30TMB Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    transistor c331

    Abstract: c331 transistor C3318 C3317 C331 C3311 C331 datasheet CY7C331 20HC c331 equivalent
    Text: CY7C331 Asynchronous Registered EPLD Features • Low power — 90 mA typical ICC quiescent • Twelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — 180 mA ICC maximum — UV-erasable and reprogrammable — One feedback flip-flop with input coming from the


    Original     		PDF CY7C331 CY7C331 transistor c331 c331 transistor C3318 C3317 C331 C3311 C331 datasheet 20HC c331 equivalent

    transistor c331

    Abstract: c331 transistor c331 c331 equivalent C3318 C3319 C3314 c3317 C3311 transistor c331 datasheet
    Text: fax id: 6016 1CY7C331 CY7C331 Asynchronous Registered EPLD Features • Low power — 90 mA typical ICC quiescent • Twelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — 180 mA ICC maximum — UV-erasable and reprogrammable


    Original     		PDF 1CY7C331 CY7C331 transistor c331 c331 transistor c331 c331 equivalent C3318 C3319 C3314 c3317 C3311 transistor c331 datasheet

    c331 equivalent

    Abstract: C3317 c331-12 c3311 192x pin diagram c331
    Text: CY7C331 Asynchronous Registered EPLD • Low power — 90 mA typical ICC quiescent Features • Twelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — 180 mA ICC maximum — UV-erasable and reprogrammable — One feedback flip-flop with input coming from the I/O


    Original     		PDF CY7C331 28-pin c331 equivalent C3317 c331-12 c3311 192x pin diagram c331

    L496D

    Abstract: 9l reset CY7C331 ST L11922 0423-J
    Text: CY7C331 -W C Y P R E S S Asynchronous Registered EPLD Features • TWelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coining from the I/O pin — Independent product term set,


    OCR Scan     		PDF CY7C331 28-pin CY7C331 -40TMB 28-Lead CY7C331â 40WMB 28-Lead 300-Mil) L496D 9l reset ST L11922 0423-J

    Untitled

    Abstract: No abstract text available
    Text: Asynchronous Registered EPLD 13 inputs, 12 feedback VO pins, plus 6 shared I/O macrocell feedbacks for a total of 31 true and complementary inpnts High speed: 20 ns maximum tpo Security bit Space-saving 28-pin slim-line DIP package; also available in 28-pin


    OCR Scan     		PDF 28-pin 28-pin termW22 28-Lead 300-Mil) CY7C331 001305b

    C3317

    Abstract: L1190 CY7331
    Text: Asynchronous Registered EPLD Features • TWelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coming from the I/O pin — Independent product term set, reset, and clock inputs on all


    OCR Scan     		PDF 28-pin 28-Lead 28-Lead 300-Mil) CY7C331 0Dlb56b C3317 L1190 CY7331

    Untitled

    Abstract: No abstract text available
    Text: CY7C332 CYPRESS Features • 12 I/O macrocells each having: — Registered, latched, or transparent array input — A choice of two clock sources — Global or local output enable OE — Up to 19 product term s (PTs) per output — Product term (PT) output polarity


    OCR Scan     		PDF CY7C332 28-Square CY7C332â 30TMB 28-Lead 30WMB 28-Lead 300-Mil)

    Untitled

    Abstract: No abstract text available
    Text: CY7C342 CY7C342B CYPRESS SEMICONDUCTOR & 128-Macrocell M A X EPLDs Features Functional Description • 128 macrocells in 8 LABs • 8 dedicated inputs, 52 bidirectional I/O pins • Programmable interconnect array • Available in 68-pin HLCC, PLCC, PGA, and Flatpack


    OCR Scan     		PDF CY7C342 CY7C342B 128-Macrocell 68-pin CY7C342/CY7C342B CY7C342/ CY7C342B Y7C342B

    CY7C342

    Abstract: No abstract text available
    Text: CY7C342 CYPRESS SEMICONDUCTOR 128-Macrocell MAX EPLDs The speed and density of the CY7C342 allows it to be used in a wide range of applications, from replacement of large amounts of 7400-series TTL logic, to complex controllers and multifunction chips. With greater than 25 times the


    OCR Scan     		PDF CY7C342 128-Macrocell 7400-series 20-pin CY7C342

    Untitled

    Abstract: No abstract text available
    Text: CY7C291A CY7C292A/CY7C293A 'W CYPRESS = SEMICONDUCTOR Reprogrammable 2K x 8 PROM Features • Windowed for reprogrammability • CMOS for optimum speed/power • High speed — 2 0 ns commercial — 25 ns (military) • Low power — 660 mW (commercial and military)


    OCR Scan     		PDF CY7C291A CY7C292A/CY7C293A 300-mil 600-mil CY7C291A, CY7C292A, CY7C293A CY7C292Aâ 35DMB CY7C293Aâ

    CY7C291A

    Abstract: CY7C292A CY7C293A 57C29
    Text: F# CYPRESS Features • Windowed for reprogrammability • CMOS for optimum speed/power • High speed — 20 ns commercial — 25 ns (military) CY7C291A CY7C292A/CY7C293A 2K X 8 Reprogrammable PROM • Direct replacement for bipolar PROMs • Capable o f withstanding >2001V stat­


    OCR Scan     		PDF CY7C291A CY7C292A/CY7C293A 300-mil 600-mil CY7C291A, CY7C292A, CY7C293A 300-mil 7C291A, 7C293A) CY7C292A 57C29

    61S11

    Abstract: No abstract text available
    Text: fax id: 6016 CY7C331 CYPRESS Asynchronous Registered EPLD Features • Twelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coming from the I/O pin — Independent product term set, reset, and clock in­


    OCR Scan     		PDF 28-pin CY7C331-30DMB CY7C331-30HMB CY7C331-30LMB CY7C331-30QMB CY7C331-- 30TMB CY7C331-30WMB CY7C331-40DMB CY7C331 61S11

    CY7C332-25HMB

    Abstract: L9646 c3328 L9806 l9634 L9680 L480 L9622 L9626 L9823
    Text: CY7C332 '0 C Y P R E S S F e a tu re s • 12 I/O macrocells each having: — Registered, latched, or transparent array input — A choice of two clock sources — Global or local output enable OE — Up to 19 product terms (PTs) per output — Product terra (PT) output polarity


    OCR Scan     		PDF CY7C332 CY7C332â 30LMB 28-Square 30TMB 28-Lead 30WMB 28-Lead CY7C332-25HMB L9646 c3328 L9806 l9634 L9680 L480 L9622 L9626 L9823

    al p13

    Abstract: CERAMIC LEADLESS CHIP CARRIER cerdip z PACKAGE cy7c291 CY7C293AL-35PC PACKAGE CERAMIC LEADLESS CHIP CARRIER LCC CY7C291A CY7C292A CY7C293A
    Text: CY7C291A CY7C292A/CY7C293A F# CYPRESS Features • Windowed for reprogrammability • CMOS for optimum speed/power • High speed — 20 ns commercial — 25 ns (military) 2K X 8 Reprogrammable PROM • Direct replacement for bipolar PROMs • Capable o f withstanding >2001V stat­


    OCR Scan     		PDF CY7C291A CY7C292A/CY7C293A 300-mil 600-mil CY7C291A, CY7C292A, CY7C293A 35QMB CY7C293A-30WMB CY7C293Aâ al p13 CERAMIC LEADLESS CHIP CARRIER cerdip z PACKAGE cy7c291 CY7C293AL-35PC PACKAGE CERAMIC LEADLESS CHIP CARRIER LCC CY7C292A

    2SUR

    Abstract: CY7C331 L1190 C3317
    Text: CY7C331 ¿F C Y P R E S S Features • TWelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coining from the I/O pin — Independent product term set, reset, and clock inpnts on all


    OCR Scan     		PDF CY7C331 28-pin 40HMB CY7C331â 40LMB 28-Square 40QMB 2SUR L1190 C3317

    7C293A

    Abstract: 7C291A
    Text: CY7C291A CY7C292A/CY7C293A î f CYPRESS Features • Windowed for reprogrammability • CMOS for optimum speed/power • High speed — 20 ns commercial 2K X 8 Reprogrammable PROM The CY7C291A, CY7C292A, and CY7C293A are plug-in replacem ents for bipolar devices and offer the advantages of


    OCR Scan     		PDF CY7C291A CY7C292A/CY7C293A 300-mil 600-mil CY7C291A, CY7C292A, CY7C293A 7C293A--50WMB 7C293A--50TMB 7C293A--50QMB 7C293A 7C291A

    Untitled

    Abstract: No abstract text available
    Text: s rs 'w CY7C332 ~ •• = Registered Combinatorial EPLD CYPRESS — SEMICONDUCTOR Features • 12 I/O macrocells each having: — Registered, latched, or transparent array input — A choice of two clock sources — Global or local output enable OE — Up to 19 product terms (PTs) per


    OCR Scan     		PDF CY7C332 CY7C332â 30QMB 30TMB 30WMB

    L9680

    Abstract: L9646
    Text: CY7C332 S r CYPRESS Features Registered Combinatorial EPLD Functional Description 13 input macrocells, each having: — Complementary input — Register, latch, or transparent access — Ttoo clock sources 15 ns tpo max. Low power — 120 mA typical Ice quiescent


    OCR Scan     		PDF CY7C332 28-Lead 28-Lead 300-Mil) 28-Pin 28-Square L9680 L9646