2CY7C1329 Search Results

CY7C1335

Abstract: No abstract text available
Text: aven’t re CY7C1335 32K x 32 Synchronous-Pipelined Cache RAM All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise is 4.2 ns 133-MHz