transistor k 316M
Abstract: NB4N316M NB4N316MDTR2G
Text: NB4N316M 3.3 V AnyLevelt Receiver to CML Driver/Translator 2.0 GHz Clock / 2.5 Gb/s Data The NB4N316M is a differential Clock or Data receiver and will accept AnyLevelt input signals: LVPECL, CML, LVCMOS, LVTTL, or LVDS. These signals will be translated to CML, operating
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NB4N316M
NB4N316M/D
transistor k 316M
NB4N316MDTR2G
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7L11M
Abstract: EP11 NB4N11M
Text: NB4N11M 3.3 V 2.5 Gb/s Multi Level Clock/Data Input to CML Receiver/ Buffer/ Translator Description T h e N B 4 N 11 M i s a d i f f e r e n t i a l 1 −t o −2 c l o c k / d a t a distribution/translation chip with CML output structure, targeted for high−speed clock/data applications. The device is functionally
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NB4N11M
LVEP11,
7L11M
NB4N11M
NB4N11M/D
EP11
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NB4N316M
Abstract: NB4N316MDTG
Text: NB4N316M 3.3 V AnyLevelt Receiver to CML Driver/Translator with Input Hysteresis 2.0 GHz Clock / 2.5 Gb/s Data http://onsemi.com The NB4N316M is a differential Clock or Data receiver and will accept AnyLevelt input signals: LVPECL, CML, LVCMOS, LVTTL, or LVDS. These signals will be translated to CML, operating
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NB4N316M
NB4N316M
NB4N316M/D
NB4N316MDTG
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Untitled
Abstract: No abstract text available
Text: NB4N11M 3.3 V 2.5 Gb/s Multi Level Clock/Data Input to CML Receiver/ Buffer/ Translator Description T h e N B 4 N 11 M i s a d i f f e r e n t i a l 1 −t o −2 c l o c k / d a t a distribution/translation chip with CML output structure, targeted for high−speed clock/data applications. The device is functionally
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NB4N11M
LVEP11,
7L11M
NB4N11M
NB4N11M/D
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Untitled
Abstract: No abstract text available
Text: NB7L111M Product Preview 2.5V / 3.3V, 6.125Gb/s 1:10 Differential Clock/Data Driver with CML Output http://onsemi.com Description The NB7L111M is a low skew 1–to–10 differential clock/data driver, designed with clock/data distribution in mind. It accepts two
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NB7L111M
125Gb/s
NB7L111M/D
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QFN-52
Abstract: AND8020 NB7L111M NB7L111MMN QFN52
Text: NB7L111M 2.5V / 3.3V, 6.125Gb/s 1:10 Differential Clock/Data Driver with CML Output Description The NB7L111M is a low skew 1–to–10 differential clock/data driver, designed with clock/data distribution in mind. It accepts two clock/data sources into multiplexer input and reproduces ten identical
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NB7L111M
125Gb/s
NB7L111M
NB7L111M/D
QFN-52
AND8020
NB7L111MMN
QFN52
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QFN-52
Abstract: QFN52 AND8020 NB7L111M NB7L111MMN 485m
Text: NB7L111M 2.5V / 3.3V, 6.125Gb/s 1:10 Differential Clock/Data Driver with CML Output Description The NB7L111M is a low skew 1–to–10 differential clock/data driver, designed with clock/data distribution in mind. It accepts two clock/data sources into multiplexer input and reproduces ten identical
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NB7L111M
125Gb/s
NB7L111M
NB7L111M/D
QFN-52
QFN52
AND8020
NB7L111MMN
485m
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Untitled
Abstract: No abstract text available
Text: NBSG53A 2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip−Flop/Clock Divider with Reset and OLS* The NBSG53A is a multi−function differential D flip−flop DFF or fixed divide by two (DIV/2) clock generator. This is a part of the GigaComm family of high performance Silicon Germanium
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NBSG53A
16-pin
NBSG53A/D
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ps2018
Abstract: No abstract text available
Text: NB4N840M 3.3V 2.7Gb/s Dual Differential Clock/Data 2 x 2 Crosspoint Switch with CML Output and Internal Termination http://onsemi.com MARKING DIAGRAM Description The NB4N840M is a high−bandwidth fully differential dual 2 x 2 crosspoint switch with CML inputs/outputs that is suitable for
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NB4N840M
NB4N840M/D
ps2018
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SY55859L
Abstract: MAX3840 NB4N840M QFN32 DB1-223 jedec package QFN-32 FOOTPRINT
Text: NB4N840M 3.3V 2.7Gb/s Dual Differential Clock/Data 2 x 2 Crosspoint Switch with CML Output and Internal Termination http://onsemi.com MARKING DIAGRAM Description The NB4N840M is a high−bandwidth fully differential dual 2 x 2 crosspoint switch with CML inputs/outputs that is suitable for
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NB4N840M
NB4N840M
NB4N840M/D
SY55859L
MAX3840
QFN32
DB1-223
jedec package QFN-32 FOOTPRINT
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ts 1620
Abstract: AND8002/D data sheet D flip flop 1005 Ic Data 25 Q 80 D flip flop IC ICs for flip flops semiconductor case marking 16 marking code onsemi counters
Text: MC100LVEL30 3.3V ECL Triple D Flip−Flop with Set and Reset The MC100LVEL30 is a triple master−slave D flip−flop with differential outputs. Data enters the master latch when the clock input is LOW and transfers to the slave upon a positive transition on the
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MC100LVEL30
MC100LVEL30
SO-20
MC100LVEL30/D
ts 1620
AND8002/D
data sheet D flip flop
1005 Ic Data
25 Q 80
D flip flop IC
ICs for flip flops
semiconductor case marking 16
marking code onsemi
counters
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Untitled
Abstract: No abstract text available
Text: NB7L11M Product Preview 2.5V/3.3V Differential 1:2 Clock/Data Fanout Buffer/ Translator with CML Outputs and Internal Termination The NB7L11M is a differential 1−to−2 clock/data distribution chip with internal source termination and CML output structure, optimized
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NB7L11M
LVEP11,
NB7L11M/D
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485G
Abstract: NB7L14M NB7L14MMN NB7L14MMNR2
Text: NB7L14M 2.5V/3.3V Differential 1:4 Clock/Data Fanout Buffer/ Translator with CML Outputs and Internal Termination The NB7L14M is a differential 1−to−4 clock/data distribution chip with internal source terminated CML output structures, optimized for minimal skew and jitter. Device produces four identical output copies
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NB7L14M
NB7L14M
NB7L14M/D
485G
NB7L14MMN
NB7L14MMNR2
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485G
Abstract: EP11 NB7L11M
Text: NB7L11M 2.5V/3.3V Differential 1:2 Clock/Data Fanout Buffer/ Translator with CML Outputs and Internal Termination The NB7L11M is a differential 1−to−2 clock/data distribution chip with internal source termination and CML output structure, optimized for low skew and minimal jitter. The device is functionally equivalent to
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NB7L11M
NB7L11M
LVEP11,
NB7L11M/D
485G
EP11
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Untitled
Abstract: No abstract text available
Text: NB7L14M Product Preview 2.5V/3.3V Differential 1:4 Clock/Data Fanout Buffer/ Translator with CML Outputs and Internal Termination The NB7L14M is a differential 1−to−4 clock/data distribution chip with internal source terminated CML output structures, optimized for
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NB7L14M
NB7L14M/D
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485G
Abstract: EP11 NB7L11M
Text: NB7L11M 2.5V/3.3V Differential 1:2 Clock/Data Fanout Buffer/ Translator with CML Outputs and Internal Termination http://onsemi.com MARKING DIAGRAM* Description The NB7L11M is a differential 1−to−2 clock/data distribution chip with internal source termination and CML output structure, optimized
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NB7L11M
NB7L11M
LVEP11,
NB7L11M/D
485G
EP11
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QFN-16
Abstract: 485G EP11 NB7L11M
Text: NB7L11M 2.5V/3.3V Differential 1:2 Clock/Data Fanout Buffer/ Translator with CML Outputs and Internal Termination http://onsemi.com MARKING DIAGRAM* Description The NB7L11M is a differential 1−to−2 clock/data distribution chip with internal source termination and CML output structure, optimized
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NB7L11M
NB7L11M
LVEP11,
NB7L11M/D
QFN-16
485G
EP11
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TRansistor 1300 free
Abstract: No abstract text available
Text: NB4L16M 2.5V/3.3V, 5 Gb/s Multi Level Clock/Data Input to CML Driver / Receiver / Buffer/ Translator with Internal Termination The NB4L16M is a differential driver/receiver/buffer/translator which can accept LVPECL, LVDS, CML, HSTL, LVCMOS/LVTTL and produce 400 mV CML output. The device is capable of receiving,
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NB4L16M
NB4L16M
NB4L16M/D
TRansistor 1300 free
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T flip flop IC
Abstract: 1005 Ic Data 3525 "application note" ECL D flip flop R S Flip Flop Latch DATASHEET FOR S-R FLIP FLOP flip flop T Toggle marking r2 so-20 Toggle flip flop IC
Text: MC100EL30 5V ECL Triple D Flip−Flop with Set and Reset The MC100EL30 is a triple master−slave D flip−flop with differential outputs. Data enters the master latch when the clock input is LOW and transfers to the slave upon a positive transition on the
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MC100EL30
MC100EL30
MC100EL30/D
T flip flop IC
1005 Ic Data
3525 "application note"
ECL D flip flop
R S Flip Flop Latch
DATASHEET FOR S-R FLIP FLOP
flip flop T Toggle
marking r2
so-20
Toggle flip flop IC
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20CML
Abstract: No abstract text available
Text: NB4L16M 2.5V/3.3V, 5 Gb/s Multi Level Clock/Data Input to CML Driver / Receiver / Buffer/ Translator with Internal Termination http://onsemi.com MARKING DIAGRAM* Description The NB4L16M is a differential driver/receiver/buffer/translator which can accept LVPECL, LVDS, CML, HSTL, LVCMOS/LVTTL
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NB4L16M/D
20CML
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MC100EL30
Abstract: MC100EL30DW
Text: MC100EL30 5V ECL Triple D Flip−Flop with Set and Reset The MC100EL30 is a triple master−slave D flip−flop with differential outputs. Data enters the master latch when the clock input is LOW and transfers to the slave upon a positive transition on the
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MC100EL30
MC100EL30
MC100EL30/D
MC100EL30DW
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2.5/PSA5R10590N
Abstract: No abstract text available
Text: TYPE PS AC Motor Start Capacitor FEA TU R ES : 1Operating Voltage: 110 VAC to 330 VAC Operating Temperatures: -40°C to +65°C Moisture & Oil Resistant Plastic Case Operating Frequency 50-60 Hz Aerovox m anufactures AC electrolytic motor starting capacitors to m eet EIA R S 463 Type
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PSA5R10590N
Abstract: Aero m capacitor
Text: ! I TYPE PS AC Motor Start Capacitor FEATURES: Operating Voltage: 110 VAC to 330 VAC Operating Temperatures: -40°C to +65°C Moisture & Oil Resistant Plastic Case Operating Frequency 50-60 Hz Aero M manufactures AC electrolytic motor starting capacitors to meet EIA RS463 Type I
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RS463
PL-10
PSA5R10590N
Aero m capacitor
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PSA5R10590N
Abstract: PSA1R1288N PSA4R22108N
Text: TYPE PS AC Motor Start Capacitor FEATURES: • • • • Operating Voltage: 110 VAC to 330 VAC Operating Temperatures: -40°C to +65°C Moisture & Oil Resistant Plastic Case Operating Frequency 50-60 Hz Aerovox manufactures AC electrolytic motor starting capacitors to meet EIA RS463 Type
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RS463
29/l6
PSA5R10590N
PSA1R1288N
PSA4R22108N
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