Untitled
Abstract: No abstract text available
Text: CY74FCT16501T CY74FCT162501T CY74FCT162H501T = # CYPR ESS Features • Low power, pin-compatible replacement for ABT functions • FCT-C speed at 4.6 ns • Power-off disable outputs permits live insertion • Edge-rate control circuitry for significantly improved noise
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CY74FCT16501T
CY74FCT162501T
CY74FCT162H501T
25-mil
CY74FCT16501T
CY74FCT162501T
18-Bit
56-Lead
240-Mil)
CY74FCT162501ATPAC
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Untitled
Abstract: No abstract text available
Text: UltraLogic 128-Macrocell Flash CPLD is designed to bring th e ease o f use and high perform ance o f th e 22V10 to highdensity CPLDs. Features • 128 macrocells in eight logic blocks • 64 I/O pins T he 128 m acrocells in th e CY7C374 are di vided betw een eight logic blocks. Each
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128-Macrocell
22V10
CY7C374
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Untitled
Abstract: No abstract text available
Text: '0 CYPRESS Features • 192 m acrocells in 12 L A B s • 8 dedicated inputs, 64 bidirectional I/O pin • Advanced 0.65-micron CMOS technology to increase performance • Programmable interconnect array • 384 expander product terms • Available in 84-pin HLCC, PLCC, and
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CY7C341B
65-micron
84-pin
CY7C341B
16perLAB.
prodB-30HMB
84-Lead
001b741
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Untitled
Abstract: No abstract text available
Text: CY7C132/CY7C136 CY7C142/CY7C146 if CYPRESS 2K x 8 Dual-Port Static RAM Functional D escription Features • 0.8-raicron CMOS for optimum speed/ power • BUSY output flag on CY7C132/ CY7C136; BUSY input on CY7C142/CY7C146 The CY7C132/CY7C136/CY7C142 and CY7C146 are high-speed CMOS 2K by 8
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CY7C132/CY7C136
CY7C142/CY7C146
CY7C132/
CY7C136;
CY7C132/CY7C136/CY7C142
CY7C146
CY7C136
CY7C142/CY7C146
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Untitled
Abstract: No abstract text available
Text: PRELIM INARY CY82C691 Pentium hyperCache™ Chipset System Controller Features • Provides control for the cache, system memory, and the PCI bus • PCI Bus Rev. 2.1 compliant • Supports 3V Pentium™, AMD K5, K6, and Cyrix 6x86 M1 CPUs • Support for WB or WT L1 cache
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CY82C691
8Kx21
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CY7C161A-15DMB
Abstract: No abstract text available
Text: CY7C161A CY7C162A 16K x 4 Static RAM with Separate I/O Functional D escription Features • High speed — 20 nstAA • CMOS for optimum speed/power • Transparent write 7C161A • Low active power — 550 mW • Low standby power — 220 mW • TTL-compatible inputs and outputs
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CY7C161A
CY7C162A
7C161A)
CY7C161A-15DMB
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Untitled
Abstract: No abstract text available
Text: /U£ho. vveune*uay, iviay 11, i«*h Revision: August 19,1994 CY7C243 CY7C244 :# C Y PR ESS 4K x 8 Reprogrammable PROM • Capable of withstanding greater than 2001V static discharge Features • CMOS for optimum speed/power The CY7C243 and CY7C244 are plug-in
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CY7C243
CY7C244
CY7C243
CY7C244
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Untitled
Abstract: No abstract text available
Text: CY7C251 CY7C254 F/ CYPRESS 16K x 8 Power-Switched and Reprogrammable PROM • Direct replacement for bipolar PROMs • Capable of withstanding > 2001V static discharge Features • CMOS for optimum speed/power • Windowed for reprogrammability • High speed
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CY7C251
CY7C254
7C251)
300-mil
600-mil
CY7C251
CY7C254
384-word
65WMB
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27H256-30
Abstract: CY27H256 H2568 27H256-55
Text: Features • CMOS for optimum speed/power • High speed — tAA = 25 ns max. commercial — tAA — 35 ns max. (military) • Low power — 275 mW max. — Less than 85 mW when deselected • Byte-wide memory organization • 100% reprogrammable in the
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CY27H256
32-pin
-28-pin
28-pin,
600-mil
27H256-30
H2568
27H256-55
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