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    1N4148

    Abstract: DS3643-1 ECL10K SP8647 GEC Plessey dg
    Text: THIS DOCUMENT IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS ADVANCE INFORMATION DS3643-1•2 SP8647 250MHz4 410/11 The SP8647 is an ECL variable modulus divider, with ECL10K and TTL/CMOS compatible outputs. It divides by 10 when either of the ECL control inputs, PE1 or PE2, is in the high


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    PDF DS3643-1 SP8647 250MHz410/11 SP8647 ECL10K 1N4148 GEC Plessey dg

    Untitled

    Abstract: No abstract text available
    Text: THIS DOCUMENT IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS ADVANCE INFORMATION DS3643-1•2 SP8647 250MHz4 410/11 The SP8647 is an ECL variable modulus divider, with ECL10K and TTL/CMOS compatible outputs. It divides by 10 when either of the ECL control inputs, PE1 or PE2, is in the high


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    PDF DS3643-1 SP8647 250MHz410/11 SP8647 ECL10K

    Untitled

    Abstract: No abstract text available
    Text: THIS DOCUMENT IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS ADVANCE INFORMATION DS3643-1•2 SP8647 250MHz4 410/11 The SP8647 is an ECL variable modulus divider, with ECL10K and TTL/CMOS compatible outputs. It divides by 10 when either of the ECL control inputs, PE1 or PE2, is in the high


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    PDF DS3643-1 SP8647 250MHz410/11 SP8647 ECL10K

    GEC PLESSEY

    Abstract: SP8647 1N4148 DS3643-1 ECL10K GEC Plessey dg
    Text: DS3643-1•2 SP8647 250MHz4 410/11 The SP8647 is an ECL variable modulus divider, with ECL10K and TTL/CMOS compatible outputs. It divides by 10 when either of the ECL control inputs, PE1 or PE2, is in the high state and by 11 when both are low or open circuit .


    Original
    PDF DS3643-1 SP8647 250MHz410/11 SP8647 ECL10K GEC PLESSEY 1N4148 GEC Plessey dg

    Untitled

    Abstract: No abstract text available
    Text: THIS DOCUMENT IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS ADVANCE INFORMATION DS3643-1•2 SP8647 250MHz4 410/11 The SP8647 is an ECL variable modulus divider, with ECL10K and TTL/CMOS compatible outputs. It divides by 10 when either of the ECL control inputs, PE1 or PE2, is in the high


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    PDF DS3643-1 SP8647 250MHz410/11 SP8647 ECL10K

    AK8122E

    Abstract: AK8122V
    Text: [AK8122] AK8122 Diffrential Zero Delay Clock Buffer AK8122 はPLL を内蔵したDDR2 メモリ対応高性能差動クロックバッファICです。 特 長 □ 電源電圧: □ 低消費電流: □ 動作周波数: □ 出力遅延: □ 低ジッタ出力:


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    PDF AK8122] AK8122 160MHzï 400MHz -30ps 100ps 190MHz-360MHz) 190MHz-250MHz) AK8122E AK8122V

    AK8122E

    Abstract: AK8122V 5122E
    Text: ASAHI KASEI EMD CORPORATION Differential Zero Delay Clock Buffer AK8122 Features Description Operational Frequency Range: 160MHz 400MHz Output delay: -30 ±100ps Low Jitter Performance: The AK8122 is a high performance differential zero delay clock buffer IC with Phase Locked Loop


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    PDF AK8122 160MHz 400MHz 100ps 360MHz) 250MHz) 300MHz) AK8122 AK8122E AK8122V 5122E

    SP8647

    Abstract: DS3643-1 1N4148 ECL10K divide-by-10 5962-90618 SP8647B
    Text: Obsolescence Notice This product is obsolete. This information is available for your convenience only. For more information on Zarlink’s obsolete products and replacement product lists, please visit http://products.zarlink.com/obsolete_products/ DS3643-1•2


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    PDF DS3643-1 SP8647 250MHz410/11 SP8647 ECL10K 1N4148 divide-by-10 5962-90618 SP8647B