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    24 BIT ADC SPI FPGA Search Results

    24 BIT ADC SPI FPGA Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TE512S32-25LC Rochester Electronics LLC TE512S32 - Field Programmable Gate Array, CMOS, PQFP128 Visit Rochester Electronics LLC Buy
    TE505S16-40QC-G Rochester Electronics LLC TE505S16 - Field Programmable Gate Array, CMOS, PQFP208 Visit Rochester Electronics LLC Buy
    TE505S16-40QI Rochester Electronics LLC TE505S16 - Field Programmable Gate Array, CMOS, PQFP208 Visit Rochester Electronics LLC Buy
    TE505S16-25QC-G Rochester Electronics LLC TE512S32 - Field Programmable Gate Array, CMOS Visit Rochester Electronics LLC Buy
    TE512S32-40LC Rochester Electronics LLC TE512S32 - Field Programmable Gate Array, CMOS, PQFP128 Visit Rochester Electronics LLC Buy

    24 BIT ADC SPI FPGA Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    12-bit ADC interface vhdl code for FPGA

    Abstract: iodelay ISERDES XC5VLX50T-FF1136.xls VHDL code for high speed ADCs using SPI with FPGA 12-bit ADC interface vhdl complete code for FPGA virtex 4 date code for ADC XAPP866 iodelay for adc parallel data and fpga interface UCF virtex-4
    Text: Application Note: Virtex-4 and Virtex-5 FPGAs R XAPP866 v3.0 April 7, 2008 An Interface for Texas Instruments Analog-to-Digital Converters with Serial LVDS Outputs Author: Marc Defossez Summary This application note describes how to interface a Texas Instruments analog-to-digital


    Original     		PDF XAPP866 12-bit ADC interface vhdl code for FPGA iodelay ISERDES XC5VLX50T-FF1136.xls VHDL code for high speed ADCs using SPI with FPGA 12-bit ADC interface vhdl complete code for FPGA virtex 4 date code for ADC XAPP866 iodelay for adc parallel data and fpga interface UCF virtex-4

    Schematic

    Abstract: DLP-2232H-SF
    Text: DLP-2232H-SF LEAD FREE USB - MICRONTROLLER - FPGA MODULE FEATURES: • • • • • • • • • • Microsemi/Actel SmartFusion Customizable System-on-Chip cSoC FPGA Internal 100MHz, 32-Bit ARM Cortex™-M3 Microcontroller Subsystem (MSS) Internal 100MHz RC Oscillator-1% Accurate


    Original     		PDF DLP-2232H-SF 100MHz, 32-Bit 100MHz 256Kbytes 64Kbytes 64-Mbit 50MHz 8/10/12-Bit 600KSPS Schematic DLP-2232H-SF

    HSM2822

    Abstract: AD9510 ADA4937-1 AN-835 AN-877 AD9284-250EBZ 09085-03
    Text: 8-Bit, 250 MSPS, 1.8 V Dual Analog-to-Digital Converter ADC AD9284 FEATURES GENERAL DESCRIPTION Single 1.8 V supply operation SNR: 49.3 dBFS at 200 MHz input at 250 MSPS SFDR: 65 dBc at 200 MHz input at 250 MSPS Low power: 314 mW at 250 MSPS On-chip reference and track-and-hold


    Original     		PDF AD9284 48-lead AD9284 4-22-2010-A CP-48-12) AD9284BCPZ-250 AD9284BCPZRL7-250 AD9284-250EBZ HSM2822 AD9510 ADA4937-1 AN-835 AN-877 AD9284-250EBZ 09085-03

    Untitled

    Abstract: No abstract text available
    Text: 8-Bit, 250 MSPS, 1.8 V Dual Analog-to-Digital Converter ADC AD9284 FEATURES GENERAL DESCRIPTION Single 1.8 V supply operation SNR: 49.3 dBFS at 200 MHz input at 250 MSPS SFDR: 65 dBc at 200 MHz input at 250 MSPS Low power: 314 mW at 250 MSPS On-chip reference and track-and-hold


    Original     		PDF AD9284 48-lead AD9284 co2-2010-A CP-48-12) AD9284BCPZ-250 AD9284BCPZRL7-250 AD9284-250EBZ

    09085-03

    Abstract: jedec package MO-220-VKKD-2
    Text: 8-Bit, 250 MSPS, 1.8 V Dual Analog-to-Digital Converter ADC AD9284 Data Sheet FEATURES GENERAL DESCRIPTION Single 1.8 V supply operation SNR: 49.3 dBFS at 200 MHz input at 250 MSPS SFDR: 65 dBc at 200 MHz input at 250 MSPS Low power: 314 mW at 250 MSPS On-chip reference and track-and-hold


    Original     		PDF 48-lead AD9284 AD9284 CP-48-12) AD9284BCPZ-250 AD9284BCPZRL7-250 AD9284-250EBZ 6-07-2012-A 09085-03 jedec package MO-220-VKKD-2

    spartan 3e vga ucf

    Abstract: 512MBDDRx4x8x16 LVCMOS33
    Text: MicroBlaze Development Kit Spartan-3E 1600E Edition User Guide UG257 v1.1 December 5, 2007 R R Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished,


    Original     		PDF 1600E UG257 LVCMOS33 spartan 3e vga ucf 512MBDDRx4x8x16 LVCMOS33

    written

    Abstract: UG230
    Text: Spartan-3E FPGA Starter Kit Board User Guide UG230 v1.2 January 20, 2011 R R Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished,


    Original     		PDF UG230 written UG230

    ug230

    Abstract: XILINX/SPARTAN 3E STARTER BOARD spartan 3e vga ucf VHDL code for ADC and DAC SPI with FPGA spartan 3 spi flash programmer schematic SPARTAN 3E STARTER BOARD xc2c64a-vq44 vhdl code for lcd of spartan3E M25P16 powertip pc1602
    Text: Spartan-3E FPGA Starter Kit Board User Guide UG230 v1.1 June 20, 2008 R R Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished,


    Original     		PDF UG230 LVCMOS33 ug230 XILINX/SPARTAN 3E STARTER BOARD spartan 3e vga ucf VHDL code for ADC and DAC SPI with FPGA spartan 3 spi flash programmer schematic SPARTAN 3E STARTER BOARD xc2c64a-vq44 vhdl code for lcd of spartan3E M25P16 powertip pc1602

    Untitled

    Abstract: No abstract text available
    Text: FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD Low power: 60 mW per channel at 80 MSPS with scalable power options SNR = 71.5 dBFS to Nyquist SFDR = 92 dBc (to Nyquist) DNL = ±0.4 LSB (typical), INL = ±0.5 LSB (typical) Serial LVDS (ANSI-644, default) Low power, reduced signal option (similar to IEEE 1596.3)


    Original     		PDF ANSI-644, AD9637 64-Lead CP-64-4

    ANSI-644

    Abstract: 5011K
    Text: FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD Low power: 60 mW per channel at 80 MSPS with scalable power options SNR = 71.5 dBFS to Nyquist SFDR = 92 dBc (to Nyquist) DNL = ±0.4 LSB (typical), INL = ±0.5 LSB (typical) Serial LVDS (ANSI-644, default) Low power, reduced signal option (similar to IEEE 1596.3)


    Original     		PDF 12-Bit, AD9637 64-Lead 091707-C CP-64-4 ANSI-644 5011K

    Untitled

    Abstract: No abstract text available
    Text: FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD Low power: 60 mW per channel at 80 MSPS with scalable power options SNR = 71.5 dBFS to Nyquist SFDR = 92 dBc (to Nyquist) DNL = ±0.4 LSB (typical), INL = ±0.5 LSB (typical) Serial LVDS (ANSI-644, default) Low power, reduced signal option (similar to IEEE 1596.3)


    Original     		PDF 12-Bit, AD9637 ANSI-644, 64-Lead CP-64-4

    Untitled

    Abstract: No abstract text available
    Text: DATA SHEET QF1D512 Simple and versatile FIR engine SavFIReTM APPLICATIONS FEATURES • Industrial Control • Maximum 512-tap symmetric or 256-tap nonsymmetric digital FIR filter with 12 – 24 bit data words and up to 32 bit coefficients • Machine Monitoring


    Original     		PDF QF1D512 512-tap 256-tap 400ksps

    QF1D512

    Abstract: adc symmetric 8bit HBM 00-07H
    Text: DATA SHEET QF1D512 Simple and versatile FIR engine SavFIReTM APPLICATIONS FEATURES • Industrial Control • Maximum 512-tap symmetric or 256-tap non- symmetric digital FIR filter with 12 – 24 bit data words and up to 32 bit coefficients • Machine Monitoring


    Original     		PDF QF1D512 512-tap 256-tap 400ksps QF1D512 adc symmetric 8bit HBM 00-07H

    AD193X-SPECIFICATIONS

    Abstract: AD1935 AD1936 AD1937 AD1938 AD1939 home theater printed circuit board st-64 AD1935XSTZ AD193X
    Text: 4 ADC/8 DAC with PLL, 192 kHz, 24 Bit CODEC AD1935/AD1936/AD1937/AD1938/AD1939 Preliminary Technical Data Features Applications PLL generated 32-192kHz or direct master clock Low EMI design 109 dB DAC/ 107dB ADC Dynamic Range and SNR -94dB THD+N Single 3.3V Supply


    Original     		PDF AD1935/AD1936/AD1937/AD1938/AD1939 32-192kHz) 107dB -94dB 24-bits 48-lead 64-lead AD193X-SPECIFICATIONS AD1935 AD1936 AD1937 AD1938 AD1939 home theater printed circuit board st-64 AD1935XSTZ AD193X

    AD1974

    Abstract: AD1974YSTZ EVAL-AD1974EB OP275
    Text: 4 ADC with PLL, 192 kHz, 24-Bit Codec AD1974 FEATURES GENERAL DESCRIPTION Phase-locked loop generated or direct master clock Low EMI design 107 dB dynamic range and SNR −94 dB THD + N Single 3.3 V supply Tolerance for 5 V logic inputs Supports 24 bits and 8 kHz to 192 kHz sample rates


    Original     		PDF 24-Bit AD1974 16-channel 48-lead AD1974 MS-026-BBC 51706-A ST-48) AD1974YSTZ EVAL-AD1974EB OP275

    Untitled

    Abstract: No abstract text available
    Text: 4 ADC with PLL, 192 kHz, 24-Bit ADC AD1974 Data Sheet FEATURES GENERAL DESCRIPTION Phase-locked loop generated or direct master clock Low EMI design 107 dB dynamic range and SNR −94 dB THD + N Single 3.3 V supply Tolerance for 5 V logic inputs Supports 24 bits and 8 kHz to 192 kHz sample rates


    Original     		PDF 16-channel 48-lead 24-Bit AD1974 AD1974 D06614-0-3/13

    WIDEBAND ULTRASOUND PULSE TRANSFORMER

    Abstract: No abstract text available
    Text: FUNCTIONAL BLOCK DIAGRAM AVDD VIN+A VIN–A VIN+B GENERAL DESCRIPTION The AD9653 is a quad, 16-bit, 125 MSPS analog-to-digital converter ADC with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 125 MSPS


    Original     		PDF 16-Bit, AD9653 AD9653BCPZ-125 AD9653BCPZRL7-125 AD9653-125EBZ 48-Lead 02-14-2011-B CP-48-13 CP-48-13 WIDEBAND ULTRASOUND PULSE TRANSFORMER

    Untitled

    Abstract: No abstract text available
    Text: FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD Low power: 55 mW per channel at 65 MSPS with scalable power options SNR = 75.5 dB to Nyquist SFDR = 91.6 dBc (to Nyquist) DNL = ±0.6 LSB (typical), INL = ±1.1 LSB (typical) Serial LVDS (ANSI-644, default) Low power, reduced signal option (similar to IEEE 1596.3)


    Original     		PDF ANSI-644, AD9257 64-Lead CP-64-4

    Untitled

    Abstract: No abstract text available
    Text: 16-Bit, 200 MSPS/250 MSPS Analog-to-Digital Converter AD9467 Preliminary Technical Data 75.5 dBFS SNR to 170 MHz at 250 MSPS @ 2.5 V p-p FS 74 dBFS SNR to 170 MHz at 250 MSPS @ 2.0 V p-p FS 90 dBFS SFDR to 300 MHz at 250 MSPS @ −1 dBFS at 2.5 V p-p FS


    Original     		PDF 16-Bit, MSPS/250 AD9467 121809-B 72-Lead CP-72-5) AD9467BCPZ-250 AD9467BCPZ-200 AD9467-200EBZ AD9467-250EBZ

    Untitled

    Abstract: No abstract text available
    Text: FUNCTIONAL BLOCK DIAGRAM AVDD VIN+A VIN–A VIN+B GENERAL DESCRIPTION The AD9653 is a quad, 16-bit, 125 MSPS analog-to-digital converter ADC with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 125 MSPS


    Original     		PDF AD9653 16-bit, MO-220-WKKD. 02-14-2011-B 48-Lead CP-48-13) AD9653BCPZ-125 AD9653BCPZRL7-125 AD9653-125EBZ

    ADCL1

    Abstract: AD1974 AD1974YSTZ AD1974YSTZ-RL OP275
    Text: 4 ADC with PLL, 192 kHz, 24-Bit ADC AD1974 FEATURES GENERAL DESCRIPTION Phase-locked loop generated or direct master clock Low EMI design 107 dB dynamic range and SNR −94 dB THD + N Single 3.3 V supply Tolerance for 5 V logic inputs Supports 24 bits and 8 kHz to 192 kHz sample rates


    Original     		PDF 24-Bit AD1974 16-channel 48-lead AD1974 MS-026-BBC 51706-A ST-48) AD1974YSTZ ADCL1 AD1974YSTZ AD1974YSTZ-RL OP275

    48-LEAD

    Abstract: AD1974 AD1974YSTZ AD1974YSTZ-RL OP275
    Text: 4 ADC with PLL, 192 kHz, 24-Bit ADC AD1974 FEATURES GENERAL DESCRIPTION Phase-locked loop generated or direct master clock Low EMI design 107 dB dynamic range and SNR −94 dB THD + N Single 3.3 V supply Tolerance for 5 V logic inputs Supports 24 bits and 8 kHz to 192 kHz sample rates


    Original     		PDF 24-Bit AD1974 16-channel 48-lead AD1974 D06614-0-2/11 AD1974YSTZ AD1974YSTZ-RL OP275

    Untitled

    Abstract: No abstract text available
    Text: 4 ADC with PLL, 192 kHz, 24-Bit ADC AD1974 FEATURES GENERAL DESCRIPTION Phase-locked loop generated or direct master clock Low EMI design 107 dB dynamic range and SNR −94 dB THD + N Single 3.3 V supply Tolerance for 5 V logic inputs Supports 24 bits and 8 kHz to 192 kHz sample rates


    Original     		PDF 24-Bit AD1974 16-channel 48-lead AD1974 D06614-0-2/11

    AD1974

    Abstract: AD1974YSTZ OP275 adc1r 5-AD1974
    Text: 4 ADC with PLL, 192 kHz, 24-Bit ADC AD1974 FEATURES GENERAL DESCRIPTION Phase-locked loop generated or direct master clock Low EMI design 107 dB dynamic range and SNR −94 dB THD + N Single 3.3 V supply Tolerance for 5 V logic inputs Supports 24 bits and 8 kHz to 192 kHz sample rates


    Original     		PDF 24-Bit AD1974 16-channel 48-lead AD1974 MS-026-BBC 51706-A ST-48) AD1974YSTZ OP275 adc1r 5-AD1974