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MMD MMC-123F-8.3223MHZ
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223MHZ Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
Untitled Abstract: No abstract text available Text: LTC2153-14 14-Bit 310Msps ADC FEATURES n n n n n n n n n n n n DESCRIPTION The LTC 2153-14 is a 310Msps 14-bit A/D converter designed for digitizing high frequency, wide dynamic range signals. It is perfect for demanding communications applications with AC performance that includes 68.8dB	Original	LTC2153-14 14-Bit 310Msps 25GHz 401mW 32VP-P 300MHz	PDF
Untitled Abstract: No abstract text available Text: LTC2158-14 Dual 14-Bit 310Msps ADC FEATURES n n n n n n n n n n n n DESCRIPTION The LTC 2158-14 is a 2-channel simultaneous sampling 310Msps 14-bit A/D converter designed for digitizing high frequency, wide dynamic range signals. It is perfect for demanding communications applications with AC performance that includes 68.8dB SNR and 88dB spurious	Original	LTC2158-14 14-Bit 310Msps 25GHz 724mW 32VP-P QFN-20	PDF
db1n Abstract: LTC6409 DB89 SDI video mixer circuit diagram LTC2158UP-12 DA11N-4 LVDS 315MHZ DA1011 LTC2158-12 DB25 DWG Text: LTC2158-12 Dual 12-Bit 310Msps ADC Features Description 67.6dBFS SNR n 88dB SFDR n Low Power: 688mW Total n Single 1.8V Supply n DDR LVDS Outputs n 1.32V P-P Input Range n 1.25GHz Full Power Bandwidth S/H n Optional Clock Duty Cycle Stabilizer n Low Power Sleep and Nap Modes	Original	LTC2158-12 12-Bit 310Msps n88dB 688mW 25GHz 14-Bit n64-Lead db1n LTC6409 DB89 SDI video mixer circuit diagram LTC2158UP-12 DA11N-4 LVDS 315MHZ DA1011 LTC2158-12 DB25 DWG	PDF
D1011 Abstract: SDI video mixer circuit diagram 47T1 N40L d8932 3-10MHz Text: LTC2153-12 12-Bit 310Msps ADC Features Description 67.6dBFS SNR n 88dB SFDR n Low Power: 378mW Total n Single 1.8V Supply n DDR LVDS Outputs n 1.32V P-P Input Range n 1.25GHz Full Power Bandwidth S/H n Optional Clock Duty Cycle Stabilizer n Low Power Sleep and Nap Modes	Original	LTC2153-12 12-Bit 310Msps n88dB 378mW 25GHz n40-Lead D1011 SDI video mixer circuit diagram 47T1 N40L d8932 3-10MHz	PDF
1008CS Abstract: DW9282 Text: DW9282 110.592MHz SAW IF Filter The DW9282 is a 110.592MHz SAW filter which has been designed for the first IF section in Digital European Cordless Telephones DECT . The filter design has resulted in an insertion loss of 12dB (max.), low group delay ripple of 100ns (typ.), with quartz temperature	Original	DW9282 592MHz DS4323-2 DW9282 100ns 1008CS	PDF
MCD2005 Abstract: 8002 AUDIO amplifier bpf 4R7 BB149 SSOP-20L PLL 100Mhz MCU programmable counter ic Phase Locked loop IC to drive VCO 4116 & FM MCD2005RX Text: MC Devices General Description Features MCD2005TX/RX is a set of ICs for FSK/FM transceiver intended for use in wireless data/audio communication, including one IC TX for transmitter and the other IC (RX) for receiver. The operating frequency covers 100MHz-500MHz.	Original	MCD2005TX/RX 100MHz-500MHz. 50ohm MCD2005 8002 AUDIO amplifier bpf 4R7 BB149 SSOP-20L PLL 100Mhz MCU programmable counter ic Phase Locked loop IC to drive VCO 4116 & FM MCD2005RX	PDF
d13n3 Abstract: LTC2153-14 LTC2153UJ-14 sck 124 442 LTC2153C LTC2153CUJ-14 LTC2153I LTC2153IUJ-14 voltage stabilizer schematic diagram mark d13n Text: Electrical Specifications Subject to Change LTC2153-14 14-Bit 310Msps ADC Features Description 68.8dBFS SNR n 88dB SFDR n Low Power: 401mW Total n Single 1.8V Supply n DDR LVDS Outputs n Easy-to-Drive 1.32V P-P Input Range n 1.25GHz Full Power Bandwidth S/H	Original	LTC2153-14 14-Bit 310Msps n88dB 401mW 25GHz 12-Bit n40-Lead d13n3 LTC2153-14 LTC2153UJ-14 sck 124 442 LTC2153C LTC2153CUJ-14 LTC2153I LTC2153IUJ-14 voltage stabilizer schematic diagram mark d13n	PDF
16 bit multiplier VERILOG Abstract: multiplier accumulator MAC code VHDL multiplier accumulator MAC code verilog vhdl code for accumulator addition accumulator MAC code verilog 16 bit multiplier VERILOG circuit multiplier accumulator unit with VHDL verilog code for 16 bit multiplier MULT18X18S XAPP636 Text: Application Note: Virtex-II Family R XAPP636 v1.4 June 24, 2004 Summary Optimal Pipelining of I/O Ports of the Virtex-II Multiplier Author: Markus Adhiwiyogo This application note and reference design describes a high-speed, optimized implementation of a Virtex -II pipelined multiplier primitive (MULT18X18 and MULT18X18S) implemented in	Original	XAPP636 MULT18X18 MULT18X18S) xapp636 16 bit multiplier VERILOG multiplier accumulator MAC code VHDL multiplier accumulator MAC code verilog vhdl code for accumulator addition accumulator MAC code verilog 16 bit multiplier VERILOG circuit multiplier accumulator unit with VHDL verilog code for 16 bit multiplier MULT18X18S	PDF
Untitled Abstract: No abstract text available Text: LTC2158-12 Dual 12-Bit 310Msps ADC FEATURES n n n n n n n n n n n n DESCRIPTION The LTC 2158-12 is a 2-channel simultaneous sampling 310Msps 12-bit A/D converter designed for digitizing high frequency, wide dynamic range signals. It is perfect for demanding communications applications with AC performance that includes 67.6dB SNR and 88dB spurious	Original	LTC2158-12 12-Bit 310Msps 25GHz 688mW 32VP-P 300MHz	PDF
Untitled Abstract: No abstract text available Text: LTC2153-12 12-Bit 310Msps ADC FEATURES n n n n n n n n n n n n DESCRIPTION The LTC 2153-12 is a 310Msps 12-bit A/D converter designed for digitizing high frequency, wide dynamic range signals. It is perfect for demanding communications applications with AC performance that includes 67.6dB	Original	LTC2153-12 12-Bit 310Msps 25GHz 378mW 32VP-P Configuration20	PDF
Untitled Abstract: No abstract text available Text: NOVEMBER 1995 PRELIMINARY INFORMATION DS4323-1•1 DW9282 • Low Insertion Loss ■ Quartz Temperature Stability ■ Balanced or Unbalanced Drive ■ Low Profile Surface Mount Package 3 GND 4 GND 5 INPUT+ 1 ABSOLUTE MAXIMUM RATINGS DC voltage Maximum input power	Original	DS4323-1Â DW9282 DW9282 592MHz 100ns 9mm37mm 10dBm	PDF
SDI video mixer circuit diagram Abstract: Amplifier gain 5000, 10000, 20000 CMRR 80dB at 50 79dBFS Text: LTC2153-14 14-Bit 310Msps ADC Features Description 68.8dBFS SNR n 88dB SFDR n Low Power: 401mW Total n Single 1.8V Supply n DDR LVDS Outputs n Easy-to-Drive 1.32V P-P Input Range n 1.25GHz Full Power Bandwidth S/H n Optional Clock Duty Cycle Stabilizer n Low Power Sleep and Nap Modes	Original	LTC2153-14 14-Bit 310Msps n88dB 401mW 25GHz 12-Bit n40-Lead SDI video mixer circuit diagram Amplifier gain 5000, 10000, 20000 CMRR 80dB at 50 79dBFS	PDF
quartz 4MHz Abstract: 110.592mhz 1008CS DW9282 FC62 Text: DW9282 110.592MHz SAW IF Filter The DW9282 is a 110.592MHz SAW filter which has been designed for the first IF section in Digital European Cordless Telephones DECT . The filter design has resulted in an insertion loss of 12dB (max.), low group delay ripple of 100ns (typ.), with quartz temperature	Original	DW9282 592MHz DS4323-2 DW9282 100ns quartz 4MHz 110.592mhz 1008CS FC62	PDF
304-MHz Abstract: 1008CS DW9282 ds432 Text: DW9282 110.592MHz SAW IF Filter • Low Group Delay Ripple ■ Low Insertion Loss ■ Quartz Temperature Stability ■ Balanced or Unbalanced Drive ■ Low Profile Surface Mount Package 3 GND 4 GND 5 ABSOLUTE MAXIMUM RATINGS DC voltage Maximum input power	Original	DW9282 592MHz DS4323-2 DW9282 100ns 10dBm 180nH 180nH, 304-MHz 1008CS ds432	PDF

mn 53100 Abstract: No abstract text available Text: w V M 53100 Y I£ d a t a s e p a r a t o r c h a n n e l c h ip 950801 FEATURES 1,7 RLL Code Data Rates From 33 to 100 Mbits/sec Compatible with Zoned-Density Recording Data Separator has Zero-Phase Restart & Marginalization Programmable Write Precompensation	OCR Scan	VM54100 64-Lead VM53100 223MHz, HP5370B 96MHz mn 53100	PDF