2048 POINT XILINX Search Results

2048 POINT XILINX Result Highlights (5)

Part	Manufacturer	Description
TCR5RG28A	Toshiba Electronic Devices & Storage Corporation	LDO Regulator, Fixed Output, 2.8 V, 500 mA, WCSP4F
TCR3DM18	Toshiba Electronic Devices & Storage Corporation	LDO Regulator, Fixed Output, 1.8 V, 300 mA, DFN4
TCR3DG18	Toshiba Electronic Devices & Storage Corporation	LDO Regulator, Fixed Output, 1.8 V, 300 mA, WCSP4E
TCR2EF18	Toshiba Electronic Devices & Storage Corporation	LDO Regulator, Fixed Output, 1.8 V, 200 mA, SOT-25 (SMV)
TCR3RM28A	Toshiba Electronic Devices & Storage Corporation	LDO Regulator, Fixed Output, 2.8 V, 300 mA, DFN4C

2048 POINT XILINX Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
verilog code for twiddle factor radix 2 butterfly Abstract: FFT CODING BY VERILOG FOR 8 POINT WITH RADIX 2 VHDL code for radix-2 fft vhdl code for FFT 32 point vhdl code for 16 point radix 2 FFT verilog code radix 4 multiplication sdc 603 vhdl code for FFT 4096 point FFT CODING BY VERILOG FOR 4 POINT WITH RADIX 2 vhdl code for radix-4 fft Text: CS2420 TM 2048/4096/8192 Point FFT/IFFT Virtual Components for the Converging World The CS2420 is an online programmable 2048 - 8192-point FFT/IFFT core. It is based on the radix-4 algorithm and performs 2048-point to 8192-point FFT/IFFT computation in three computation passes. A block diagram of the	Original	CS2420 CS2420 8192-point 2048-point 4096x32 8/16-point 8192-point verilog code for twiddle factor radix 2 butterfly FFT CODING BY VERILOG FOR 8 POINT WITH RADIX 2 VHDL code for radix-2 fft vhdl code for FFT 32 point vhdl code for 16 point radix 2 FFT verilog code radix 4 multiplication sdc 603 vhdl code for FFT 4096 point FFT CODING BY VERILOG FOR 4 POINT WITH RADIX 2 vhdl code for radix-4 fft	PDF
radix-8 FFT Abstract: 2048-point IFFT radix-2 CS2420 CS2421 2048-POINT xilinx radix-2 fft xilinx Text: CS2421 TM 2048/8192-Point IFFT Preliminary Datasheet Virtual Components for the Converging World The CS2421 is an online programmable, 2048/8192-point Inverse Fast Fourier Transform IFFT core. This highly integrated application specific silicon core is based on the radix-4 algorithm and performs 2048-point or 8192point IFFT algorithms in three computation passes. The CS2421 IFFT core is available in both ASIC and FPGA	Original	CS2421 2048/8192-Point CS2421 2048-point 8192point DS2421 radix-8 FFT IFFT radix-2 CS2420 2048-POINT xilinx radix-2 fft xilinx	PDF
2-bit half adder Abstract: FPGA based implementation of fixed point IIR Filter XC4025 xilinx FPGA implementation of IIR Filter digital FIR Filter using distributed arithmetic Text: The Role of Distributed Arithmetic in FPGA-based Signal Processing Introduction Distributed Arithmetic DA plays a key role in embedding DSP functions in the Xilinx 4000 family of FPGA devices. In this document the DA algorithm is derived and examples are offered that illustrate its	Original		PDF
radix-4 DIT FFT C code Abstract: DS260 radix-2 fft xilinx DS-260 radix-2 2048 point xilinx XC2V3000 XC2VP20 radix4 Text: Fast Fourier Transform v2.0 DS260 v2.0 July 14, 2003 Features • Drop-in module for Virtex -II, Virtex-II Pro™, and Spartan™-3 FPGAs • Forward and inverse complex FFT • Transform sizes N = 2m, m = 4 – 14 • Data sample precision bx = 8,12,16,20,24	Original	1024-point DS260 radix-4 DIT FFT C code DS260 radix-2 fft xilinx DS-260 radix-2 2048 point xilinx XC2V3000 XC2VP20 radix4	PDF
virtex 5 fpga based image processing Abstract: FRACTIONAL INTERPOLATOR abstract for wireless technology in ieee format Polyphase Filter Banks Text: Real Time Image Rotation and Resizing, Algorithms and Implementations Robert D. Turney and Chris H. Dick CORE SOLUTIONS GROUP, XILINX, INC. 2100 LOGIC DRIVE SAN JOSE, CA 95124-3450 ABSTRACT Recent growth in the area of digital communications has been fueled by new and	Original	May1999. virtex 5 fpga based image processing FRACTIONAL INTERPOLATOR abstract for wireless technology in ieee format Polyphase Filter Banks	PDF
1736DPC Abstract: xilinx 1736DPC pinout BNC -rj45 bzx85c MOTOROLA MC68HC11 interface board block diagram RJ45 to rs232 DB9 cable adapter pinout analog DIODE ST2 fireberd 6000 fireberd 6000 parts list MC68HC11E9 Text: Freescale Semiconductor, Inc. MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC145574EVK Advance Information ISDN S/T Interface Transceiver Evaluation Kit EIA-232 PROM MC145407 SCP MC68HC11E9 XILINX MicroController XC3020A BERT Clk SCP IDL IDL IDL MC145574 ISDN S/T Interface	Original	MC145574EVK EIA-232 MC145407 MC68HC11E9 XC3020A MC145574 MC145574EVK MC145407P 1736DPC xilinx 1736DPC pinout BNC -rj45 bzx85c MOTOROLA MC68HC11 interface board block diagram RJ45 to rs232 DB9 cable adapter pinout analog DIODE ST2 fireberd 6000 fireberd 6000 parts list MC68HC11E9	PDF
IGBT rectifier theory Abstract: No abstract text available Text: IRMCx201 Application Developer’s Guide October 1, 2003 Version 4.0A IRMCx201 Application Developer’s Guide Table of Contents 1 Introduction. 5	Original	IRMCx201 IRMCx201 IGBT rectifier theory	PDF
ICCT2000 Abstract: marconi 4200 MTL 5541 ifr 4200 panel marconi+4200+tester+manual HP3070 Text: ATE 4230 Advanced Manufacturing Test System A compact rack mounted version of the successful 4250 Advanced Manufacturing Test System • Maximum of 2048 test pins System Overview • Compact 19 inch vertical rack • Built-in PC system controller • Microsoft WindowsTM operating system	Original	19-inch ICCT2000 marconi 4200 MTL 5541 ifr 4200 panel marconi+4200+tester+manual HP3070	PDF
XAPP753 Abstract: ISERDES OSERDES TMSC6000 RAMB16 TMS320C64xx cpu XC4VLX25 microblaze block architecture IPC-2141 NEWNES RADIO Text: Interfacing Xilinx FPGAs to TI DSP Platforms Using the EMIF Application Note XAPP753 v2.0.1 January 29, 2007 R R Xilinx is disclosing this Specification to you solely for use in the development of designs to operate on Xilinx FPGAs. Except as stated herein,	Original	XAPP753 IPC-2141 IPC-D-317A, 0-13-084408-x) XAPP753 ISERDES OSERDES TMSC6000 RAMB16 TMS320C64xx cpu XC4VLX25 microblaze block architecture NEWNES RADIO	PDF
str 5653 Abstract: STR - Z 2757 STR M 6545 16 point FFT radix-4 VHDL documentation radix-2 DIT FFT vhdl program STR G 5653 STR F 5653 xc6slx150t RTL 8376 matlab code for radix-4 fft Text: Fast Fourier Transform v7.0 DS260 June 24, 2009 Product Specification Introduction Overview The Xilinx LogiCORE IP Fast Fourier Transform FFT implements the Cooley-Tukey FFT algorithm, a computationally efficient method for calculating the Discrete Fourier Transform (DFT).	Original	DS260 str 5653 STR - Z 2757 STR M 6545 16 point FFT radix-4 VHDL documentation radix-2 DIT FFT vhdl program STR G 5653 STR F 5653 xc6slx150t RTL 8376 matlab code for radix-4 fft	PDF
Cannon connectors Abstract: smema smema specifications 8002 amplifier A-100 F-100 smema control Text: ATE 4200 Series Advanced Manufacturing Test Systems A range of advanced manufacturing test systems offering a wide range of test methods and high throughput capability. • Maximum of 2048 pins Architecture • Windows 95 or NT operating system • Automatic program generation software	Original		PDF
chipscope manual Abstract: MultiLINX XC2064 Parallel Cable III 11290 Text: R ChipScope Software and ILA Cores User Manual 0401884 v2.0 December 15, 2000 Software v2001.1 ChipScope Software and ILA Cores User Manual — 0401884 v2.0 Printed in U.S.A. ChipScope Software and ILA Cores User Manual — 0401884 v2.0 R The Xilinx logo shown above is a registered trademark of Xilinx, Inc.	Original	v2001 XC2064, XC3090, XC4005, XC5210, XC-DS501 chipscope manual MultiLINX XC2064 Parallel Cable III 11290	PDF
x24103030600 Abstract: XAPP241 XCV405E XCV812E XVC405E Text: Application Note: Virtex-EM Family Virtex-EM FIR Filter for Video Applications R Author: Ralf Kreuger XAPP241 v1.0 March 14, 2000 Summary Virtex -E Extended Memory (Virtex-EM) FPGA devices offer over a million bits of block RAM and up to 300 Kb of distributed RAM in a single high-performance device. This is ideal for highbandwidth video applications where complex digital filtering logic can operate on several lines	Original	XAPP241 x24103030600 XAPP241 XCV405E XCV812E XVC405E	PDF
XAPP241 Abstract: virtex 6 fpga based image processing Parallel FIR Filter x24103030600 implementation of data convolution algorithms digital FIR Filter using multiplier X241 XCV405E XCV812E XVC405E Text: Application Note: Virtex-EM Family Virtex-EM FIR Filter for Video Applications R Author: Ralf Kreuger XAPP241 v1.1 October 3, 2000 Summary Virtex -E Extended Memory (Virtex-EM) FPGA devices offer over a million bits of block RAM and up to 300 Kb of distributed RAM in a single high-performance device. This is ideal for highbandwidth video applications where complex digital filtering logic can operate on several lines	Original	XAPP241 XAPP241 virtex 6 fpga based image processing Parallel FIR Filter x24103030600 implementation of data convolution algorithms digital FIR Filter using multiplier X241 XCV405E XCV812E XVC405E	PDF

xilinx tri mode ethernet TRANSMITTER signal Abstract: ML505 DVB T transport stream processor vhdl pid tx2/rx2 w2C65 application TEMAC xilinx vhdl rs232 code 202-222 w20DF Text: Video Over IP User Guide UG463 v2.0 January 20, 2009 R R Disclaimer: Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the	Original	UG463 xilinx tri mode ethernet TRANSMITTER signal ML505 DVB T transport stream processor vhdl pid tx2/rx2 w2C65 application TEMAC xilinx vhdl rs232 code 202-222 w20DF	PDF
xc6slx150t Abstract: STR Y 6763 64 point FFT radix-4 VHDL documentation 16 point FFT radix-4 VHDL documentation verilog code for radix-4 complex fast fourier transform radix-2 DIT FFT vhdl program fft matlab code using 8 point DIT butterfly str 1096 XC6VLX75T vhdl code for simple radix-2 Text: LogiCORE IP Fast Fourier Transform v8.0 DS808 July 25, 2012 Product Specification Introduction LogiCORE IP Facts The Xilinx LogiCORE IP Fast Fourier Transform FFT implements the Cooley-Tukey FFT algorithm, a computationally efficient method for calculating the	Original	DS808 xc6slx150t STR Y 6763 64 point FFT radix-4 VHDL documentation 16 point FFT radix-4 VHDL documentation verilog code for radix-4 complex fast fourier transform radix-2 DIT FFT vhdl program fft matlab code using 8 point DIT butterfly str 1096 XC6VLX75T vhdl code for simple radix-2	PDF
Untitled Abstract: No abstract text available Text: FEATURES FUNCTIONAL BLOCK DIAGRAM REGCAP Fast throughput rate of 1 MSPS Specified for VDD of 2.7 V to 5.25 V Logic voltage VDRIVE of 1.65 V to 5.25 V INL of ±1 LSB maximum Analog input range of 0 V to VREF Ultralow power 349 µA typical at 3 V and 1 MSPS	Original	10-lead, 10-lead oscillato7091RBCPZ-RL AD7091RBCPZ-RL7 AD7091RBRMZ AD7091RBRMZ-RL7 EVAL-AD7091RSDZ	PDF
park and clark transformation Abstract: HP35665 verilog for ac servo motor encoder PWM simulation matlab 16 bit Array multiplier code in VERILOG analog servo controller for bldc verilog for park transformation resolver Matlab BLDC 3 phase BLDC motor control MATLAB PWM matlab Text: New Digital Hardware Control Method for High Performance AC Servo Motor Drive – AcceleratorTM Servo Drive Development Platform for Military Application Toshio Takahashi, International Rectifier As presented at Military Electronics Conference, Sept 24-25, 2002	Original		PDF
d5200c Abstract: RAMB16BWER vhdl code SECDED Xilinx ISE Design Suite 14.2 XC6SLX45T RAMB18E1 Text: LogiCORE IP AXI Block RAM BRAM Controller (v1.03a) DS777 July 25, 2012 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP AXI Block RAM (BRAM) Controller is a soft IP core for use with the Xilinx Vivado™ Design Suite, Embedded Development Kit	Original	DS777 ZynqTM-7000 d5200c RAMB16BWER vhdl code SECDED Xilinx ISE Design Suite 14.2 XC6SLX45T RAMB18E1	PDF
CS3411 Abstract: Viterbi Decoder CS3410 viterbi IESS-308/309 CS3311 IESS-308 Convolutional Encoder details and application CSC3411AA base-10 Text: CS3411 TM High Speed Viterbi Decoder Virtual Components for the Converging World The CS3411 Viterbi Decoder is a high performance implementation suitable for a range of Forward Error Correction applications. This highly integrated application specific core can be used in conjunction with other	Original	CS3411 CS3411 CS3311 DS3411 Viterbi Decoder CS3410 viterbi IESS-308/309 CS3311 IESS-308 Convolutional Encoder details and application CSC3411AA base-10	PDF
riacon Abstract: XC1736DPD8C 503AHL robinson-nugent 74HCT541N LI-500 riacon* 6 pin male connector Text: DEM-DDC112U-C EVALUATION FIXTURE FEATURES DESCRIPTION ● EASY INSTALLATION AND USE The DEM-DDC112U-C Evaluation Fixture is designed for ease of use when evaluating the DDC112 precision integrating analog-to-digital converter. This kit includes a PC Interface board and DUT board, allowing the user	Original	DEM-DDC112U-C DDC112 OT-23 25-Line 25-Pin 34-Line 34-Pin riacon XC1736DPD8C 503AHL robinson-nugent 74HCT541N LI-500 riacon* 6 pin male connector	PDF
503ahl Abstract: hp laserjet 1000 circuit printer hp laserjet 1000 circuit Robinson Nugent idh sensor 3414 31024102 laserjet 4 diode LM4040AIM-4 Robinson Nugent idh-34lp XC3042-70 Text: DEM-DDC112U-C EVALUATION FIXTURE FEATURES DESCRIPTION ● EASY INSTALLATION AND USE The DEM-DDC112U-C evaluation fixture is designed for ease of use when evaluating the DDC112 precision integrating analog-to-digital converter. This kit includes a PC interface board and DUT board, allowing for	Original	DEM-DDC112U-C DEM-DDC112U-C DDC112 DDC112U 25-Pin 34-Pin 25-Line 503ahl hp laserjet 1000 circuit printer hp laserjet 1000 circuit Robinson Nugent idh sensor 3414 31024102 laserjet 4 diode LM4040AIM-4 Robinson Nugent idh-34lp XC3042-70	PDF
TAG 8738 Abstract: code for mpeg-4 Macroblock planar YUV display vhdl spartan 3a Variable Length Decoder VLD yuv rgb vhdl VHDL code motion Text: - THIS IS A DISCONTINUED IP CORE - MPEG-4 Simple Profile Decoder v1.3 DS338 v1.7 April 14, 2008 Product Specification Introduction Applications The Xilinx LogiCORETM IP MPEG-4 Part 2 Simple Profile Decoder core is a fully functional VHDL design implemented on a Xilinx FPGA. The MPEG-4 Decoder	Original	DS338 TAG 8738 code for mpeg-4 Macroblock planar YUV display vhdl spartan 3a Variable Length Decoder VLD yuv rgb vhdl VHDL code motion	PDF
az5281 Abstract: ADS5282 ads5282 transformer xilinx 1200 QFN-64 XAPP774 ADS5281 HTQFP-80 Text: ADS5281 ADS5282 www.ti.com SBAS397H – DECEMBER 2006 – REVISED MARCH 2008 12-Bit Octal-Channel ADC Family Up to 65MSPS DESCRIPTION LVDD 1.8V LCLKN 12x ADCLK PLL ADCLKP 1x ADCLK ADCLKN PowerDown Channels 2 to 7 OUT8P OUT8N Drive Current ADC Control PD	Original	ADS5281 ADS5282 SBAS397H 12-Bit 65MSPS 12-Bit az5281 ADS5282 ads5282 transformer xilinx 1200 QFN-64 XAPP774 ADS5281 HTQFP-80	PDF

2048 POINT XILINX Search Results

2048 POINT XILINX Result Highlights (5)

2048 POINT XILINX Datasheets Context Search

verilog code for twiddle factor radix 2 butterfly

radix-8 FFT

2-bit half adder

radix-4 DIT FFT C code

virtex 5 fpga based image processing

1736DPC

IGBT rectifier theory

ICCT2000

XAPP753

str 5653

Cannon connectors

chipscope manual

x24103030600

XAPP241

xilinx tri mode ethernet TRANSMITTER signal

xc6slx150t

Untitled

park and clark transformation

d5200c

CS3411

riacon

503ahl

TAG 8738

az5281