MC10170
Abstract: MC10160 MC10170FN MC10170L MC10170P
Text: MC10170 9+2-Bit Parity Generator/ Checker The MC10170 is a 11–bit parity circuit, which is segmented into 9 data bits and 2 control bits. Output A generates odd parity on 9 bits; that is, Output A goes high for an odd number of high logic levels on the bit inputs in only 2 gate
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MC10170
MC10170
MC10160
r14525
MC10170/D
MC10170FN
MC10170L
MC10170P
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MC10170
Abstract: T315 MC10170L
Text: MC10170 9+2-Bit Parity Generator/ Checker The MC10170 is a 11–bit parity circuit, which is segmented into 9 data bits and 2 control bits. Output A generates odd parity on 9 bits; that is, Output A goes high for an odd number of high logic levels on the bit inputs in only 2 gate
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MC10170
MC10160
80ain
T315
MC10170L
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Untitled
Abstract: No abstract text available
Text: IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE 28-BIT 1:2 REGISTERED BUFFER WITH PARITY IDT74SSTU32865 FEATURES: DESCRIPTION: • • • • • • • The SSTU32865 is a 28-bit 1:2 configurable registered buffer designed
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IDT74SSTU32865
28-BIT
IDT74SSTU32865
100mA
MIL-STD-883,
200pF,
160-pin
SSTU32865
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DL122
Abstract: MC10160 MC10170
Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 9+2-Bit Parity Generator/ Checker MC10170 The MC10170 is a 11–bit parity circuit, which is segmented into 9 data bits and 2 control bits. Output A generates odd parity on 9 bits; that is, Output A goes high for an odd number of high logic levels on the bit inputs in only 2 gate delays.
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MC10170
MC10170
MC10160
MC10170/D*
MC10170/D
DL122
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ICS98ULPA877A
Abstract: IDT74SSTUBF32865A IDTCSPUA877A Q19A
Text: DATASHEET IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Description The IDT74SSTUBF32865A includes a parity checking function. The IDT74SSTUBF32865A accepts a parity bit from the memory controller at its input pin PARIN, compares it with the data received on the D-inputs and
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IDT74SSTUBF32865A
28-BIT
IDT74SSTUBF32865A
199707558G
ICS98ULPA877A
IDTCSPUA877A
Q19A
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ICS98ULPA877A
Abstract: IDT74SSTUBF32865A IDTCSPUA877A Q19A
Text: DATASHEET IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Description The IDT74SSTUBF32865A includes a parity checking function. The IDT74SSTUBF32865A accepts a parity bit from the memory controller at its input pin PARIN, compares it with the data received on the D-inputs and
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IDT74SSTUBF32865A
28-BIT
IDT74SSTUBF32865A
199707558G
ICS98ULPA877A
IDTCSPUA877A
Q19A
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160-ball
Abstract: No abstract text available
Text: DATASHEET IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Description The IDT74SSTUBF32865A includes a parity checking function. The IDT74SSTUBF32865A accepts a parity bit from the memory controller at its input pin PARIN, compares it with the data received on the D-inputs and
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28-BIT
IDT74SSTUBF32865A
IDT74SSTUBF32865A
74SSTUBF32865ABK
BK160)
74SSTUBF32865ABK8
160-ball
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Untitled
Abstract: No abstract text available
Text: DATASHEET IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Description The IDT74SSTUBF32865A includes a parity checking function. The IDT74SSTUBF32865A accepts a parity bit from the memory controller at its input pin PARIN, compares it with the data received on the D-inputs and
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IDT74SSTUBF32865A
28-BIT
IDT74SSTUBF32865A
199707558G
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IDT74SSTU32865
Abstract: SSTU32865
Text: IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE 28-BIT 1:2 REGISTERED BUFFER WITH PARITY FEATURES: IDT74SSTU32865 DESCRIPTION: • • • • • • • 1.8V Operation SSTL_18 style clock and data inputs Differential CLK input
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IDT74SSTU32865
28-BIT
100mA
MIL-STD-883,
200pF,
160-pin
SSTU32865
IDT74SSTU32865
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DDR3U
Abstract: SSTE32882 2yn1 DDR3 rdimm pcb layout SSTE32882KA1 DDR3U-1600 da-15 pinout dba1 DDR3 layout DDR3 pcb layout
Text: DATASHEET Advanced Information 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Description This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock driver with parity is designed for 1.25V, 1.35V and 1.5V VDD operation.
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28-bit
26-bit
32882KA1
SSTE32882KA1
DDR3U
SSTE32882
2yn1
DDR3 rdimm pcb layout
SSTE32882KA1
DDR3U-1600
da-15 pinout
dba1
DDR3 layout
DDR3 pcb layout
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SSTE32882KA1
Abstract: No abstract text available
Text: DATASHEET Advanced Information 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Description This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock driver with parity is designed for 1.25V, 1.35V and 1.5V VDD operation.
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28-bit
26-bit
32882KA1
SSTE32882KA1
SSTE32882KA1
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Untitled
Abstract: No abstract text available
Text: IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE 28-BIT 1:2 REGISTERED BUFFER WITH PARITY FEATURES: IDT74SSTU32865 DESCRIPTION: • • • • • • • 1.8V Operation SSTL_18 style clock and data inputs Differential CLK input
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IDT74SSTU32865
28-BIT
IDT74SSTU32865
100mA
MIL-STD-883,
200pF,
160-pin
CSPU877/A/D
DDR2-400/533
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Untitled
Abstract: No abstract text available
Text: IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE 28-BIT 1:2 REGISTERED BUFFER WITH PARITY FEATURES: IDT74SSTU32865 DESCRIPTION: • • • • • • • 1.8V Operation SSTL_18 style clock and data inputs Differential CLK input
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IDT74SSTU32865
28-BIT
100mA
MIL-STD-883,
200pF,
160-pin
SSTU32865
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MC10170
Abstract: la 116 diagram
Text: M O TO R O LA 9 + 2-BIT PARITY G ENERATO R-CH ECKER 9 + 2-BIT PARITY GENERATOR-CHECKER The MC10170 is a 11-bit parity circuit, which is segmented into 9 data bits and 2 control bits. Output A generates odd parity on 9 bits; that is, Output A goes high for an odd number of high logic levels on the bit inputs in
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MC10170
11-bit
MC10160
MC10170
50-ohm
la 116 diagram
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MC-10170
Abstract: No abstract text available
Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 9+2-Bit Parity Generator/ Checker MCI 0170 The MC10170 is a 11-bit parity circuit, which is segmented into 9 data bits and 2 control bits. Output A generates odd parity on 9 bits; that is, Output A goes high for an odd number of high logic levels on the bit inputs in only 2 gate delays.
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MC10170
11-bit
MC10160
50-ohm
DL122
MC-10170
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OB-90
Abstract: No abstract text available
Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 9+2-Bit Parity Generator/ Checker MC10170 The MC10170 is a 11-bit parity circuit, which is segmented into 9 data bits and 2 control bits. Output A generates odd parity on 9 bits; that is, Output A goes high for an odd number of high logic levels on the bit inputs in only 2 gate delays.
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MC10170
11-bit
MC10160
MC10170
50-ohm
DL122
OB-90
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Untitled
Abstract: No abstract text available
Text: 74AC11286 9-BIT PARITY GENERATOR/CHECKER WITH BUS DRIVER PARITY I/O PORTS _ D3165, AUGUST 1988 - REVISED APRIL 1993 D OR N PACKAGE TOP VIEW * Generates Either Odd or Even Parity for Nine Data Unes * Cascadabie for n-Bits Parity B[ 1 At 2 * Direct Bus Connection for Parity
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74AC11286
D3165,
500-mA
300-mil
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KAG 17 127
Abstract: No abstract text available
Text: M M O T O R O LA Military 10570 9 + 2-Bit Parity Generator-Checker ELECTRICALLY TESTED PER: MPG 10570 The 10570 is a 11-bit parity circuit, which is segmented into 9 data bits and 2 control bits. Output A generates odd parity on 9-bits; that is, Output A go e s high
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11-bit
KAG 17 127
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Untitled
Abstract: No abstract text available
Text: SN 54 A S286 , SN 74 A S286 9 BIT PARITY GENERATORS/CHECKER WITH BUS DRIVER PARITY 110 PORT D 2 8 0 9 , DECEM BER 1 9 8 3 - • Generates Either Odd or Even Parity for Nine Data Lines • Cascadable for n-Bits Parity • Direct Bus Connection for Parity Generation
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300-mil
74AS28G
AS286
90-BIT
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Untitled
Abstract: No abstract text available
Text: Q3283T • LS0112B □ □ 7 T 7 2 7 bl4 ■ NSC1 53 National Semiconductor 74ACTQ3283T 32-Bit Latchable Transceiver with Parity Generator/Parity Checker and Byte Multiplexing with TRI-STATE Outputs General Description Features T h e 'AC TQ 3283T is a 32-bit latchable transceiver w ith parity
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Q3283T
LS0112B
74ACTQ3283T
32-Bit
3283T
16-bit
007T7MS
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Untitled
Abstract: No abstract text available
Text: HITACHI/ L O G IC/ AR RA YS /M EN ^5 74 HC180 HD D Ë | 4 4 ^ 5 0 3 001 0425 O 92D 1 0 4 2 5 # 8-bit O dd/Even Parity G enerator/C hecker This universal, monolithic, 9-bit 8 data bits plus 1 parity bit parity generator/checker features odd/even outputs and
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HC180
0D1D315
T-90-20
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g0517
Abstract: No abstract text available
Text: NATIONAL SEMICOND {LOGIC* t,l SEMICONDUCTOR 61C 5 1 7 2 4 7- 4 5 - / ? - g g National À jà Semiconductor PRELIM" DM54AS280/DM74ÀS280 9-Bit Parity Generator/Checker General Description These universal, 9-bit parity generators/checkers utilize •
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DM54AS280/DM74AS280
DM54AS280/DM74
AS280
bS01122
005172b
DM54AS280/
DM74AS280
TU/F/6303-2
AS280s
g0517
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Untitled
Abstract: No abstract text available
Text: ADVANCE INFORMATION SN 54F280A, SN 74F2B0A 9 BIT PARITY GENERATORS/CHECKERS 0 2 9 3 2 , M AR C H 1 9 8 7 Generates Either Odd or Even Parity for Nine Data Lines SN 54F2B0A . . J PACKAGE SN 74F280A . . . D OR N PACKAGE TOP VIEW Cascadable for n-Bits Parity
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54F280A,
74F2B0A
300-mil
54F2B0A
74F280A
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s286
Abstract: No abstract text available
Text: SN54AS286, SN74AS2B6 9 BIT PARITY GENERATORS/CHECKER WITH BUS DRIVER PARITY I/O PORT D 2 8 0 9 , DECEMBER 1 9 8 3 ~ REVISED AU G U S T 1 9 8 5 • Generates Either Odd or Even Parity for Nine Data Lines • Cascadable for n-Bits Parity S N 54A S286 . . J PACKAGE
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SN54AS286,
SN74AS2B6
SN74AS286
s286
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