1CY7C1372BV25 Search Results

TMS 3766

Abstract: DPA 51 7C1370
Text: 1CY7C1372BV25 CY7C1370BV25 CY7C1372BV25 PRELIMINARY 512Kx36/1Mx18 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between write and read cycles • Fast clock speed: 200, 180,166, 150, and 133 MHz • Fast access time: 3.0,3.2,3.4, 3.8, 4.2 ns