jpeg decompression algorithm
Abstract: ethernet card schematic camera schematic diagrams SCHEMATIC ip camera on board tft monitor schematic ARM966E-S ip camera STR91XFAW
Text: STEVAL-PCC008V1 TFT display demonstration board with Ethernet connectivity based on the STR91 Data brief Features • Embedded Ethernet web client based on the STR91 system package ■ Board fitted with TFT, microSD card, and keypad ■ System pre-programmed
|
Original
|
PDF
|
STEVAL-PCC008V1
STR91
STR91
STEVAL-PCC008V1
STR91xFAW
ARM966E-STM
16/32-Bit
jpeg decompression algorithm
ethernet card schematic
camera schematic diagrams
SCHEMATIC ip camera on board
tft monitor schematic
ARM966E-S
ip camera
|
Untitled
Abstract: No abstract text available
Text: STEVAL-PCC008V1 TFT display demonstration board with Ethernet connectivity based on the STR91 Data brief Features • Embedded Ethernet web client based on the STR91 system package ■ Board fitted with TFT, microSD card, and keypad ■ System pre-programmed
|
Original
|
PDF
|
STEVAL-PCC008V1
STR91
STR91
STEVAL-PCC008V1
STR91xFAW
ARM966E-Sâ
16/32-Bit
|
SN54GTL16923
Abstract: SN74GTL16923
Text: SN54GTL16923, SN74GTL16923 18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVERS SCBS674C – AUGUST 1996 – REVISED MARCH 1997 D D D D D 1 64 2 63 3 62 4 61 5 60 6 59 7 58 8 57 9 56 10 55 11 54 12 53 13 52 14 51 15 50 16 49 17 48 18 47 19 46 20 45 21 44 22 43 23 42
|
Original
|
PDF
|
SN54GTL16923,
SN74GTL16923
18-BIT
SCBS674C
SN54GTL16923
SN74GTL16923
|
SN74GTL16922
Abstract: SN54GTL16922
Text: SN54GTL16922, SN74GTL16922 18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVERS SCBS673A – AUGUST 1996 – REVISED NOVEMBER 1996 D D D D D 1 64 2 63 3 62 4 61 5 60 6 59 7 58 8 57 9 56 10 55 11 54 12 53 13 52 14 51 15 50 16 49 17 48 18 47 19 46 20 45 21 44 22 43 23
|
Original
|
PDF
|
SN54GTL16922,
SN74GTL16922
18-BIT
SCBS673A
SN74GTL16922
SN54GTL16922
|
Untitled
Abstract: No abstract text available
Text: SN54GTL16923, SN74GTL16923 18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVERS SCBS674D – AUGUST 1996 – REVISED JULY 1997 D D D D D Members of the Texas Instruments Widebus Family Translate Between GTL/GTL+ Signal Levels and LVTTL or 5-V TTL Signal Levels Support Mixed-Mode Signal Operation on
|
Original
|
PDF
|
SN54GTL16923,
SN74GTL16923
18-BIT
SCBS674D
MIL-STD-883,
SN74GTL16923
|
SN54GTL16622
Abstract: SN74GTL16622
Text: SN54GTL16622, SN74GTL16622 18-BIT LVTTL-TO-GTL/GTL+ TRANSCEIVERS SCES049C – AUGUST 1995 – REVISED OCTOBER 1996 D D D D 1 64 2 63 3 62 4 61 5 60 6 59 7 58 8 57 9 56 10 55 11 54 12 53 13 52 14 51 15 50 16 49 17 48 18 47 19 46 20 45 21 44 22 43 23 42 24 41
|
Original
|
PDF
|
SN54GTL16622,
SN74GTL16622
18-BIT
SCES049C
SN54GTL16622
SN74GTL16622
|
SN54GTL16622
Abstract: SN74GTL16622
Text: SN54GTL16622, SN74GTL16622 18-BIT LVTTL-TO-GTL/GTL+ TRANSCEIVERS SCES049C – AUGUST 1995 – REVISED OCTOBER 1996 D D D D 1 64 2 63 3 62 4 61 5 60 6 59 7 58 8 57 9 56 10 55 11 54 12 53 13 52 14 51 15 50 16 49 17 48 18 47 19 46 20 45 21 44 22 43 23 42 24 41
|
Original
|
PDF
|
SN54GTL16622,
SN74GTL16622
18-BIT
SCES049C
SN54GTL16622
SN74GTL16622
|
Untitled
Abstract: No abstract text available
Text: SN54GTL16622A, SN74GTL16622A 18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVERS SCBS673C – AUGUST 1996 – REVISED NOVEMBER 1999 D D D D D D D D D D Members of the Texas Instruments Widebus Family D-Type Flip-Flops With Qualified Storage Enable Translate Between GTL/GTL+ Signal Levels
|
Original
|
PDF
|
SN54GTL16622A,
SN74GTL16622A
18-BIT
SCBS673C
000-V
A114-A)
A115-A)
|
A115-A
Abstract: C101 GTL16622A SN54GTL16622A SN74GTL16622A
Text: SN54GTL16622A, SN74GTL16622A 18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVERS SCBS673D – AUGUST 1996 – REVISED DECEMBER 1999 D D D D D D D D D D Members of the Texas Instruments Widebus Family D-Type Flip-Flops With Qualified Storage Enable Translate Between GTL/GTL+ Signal Levels
|
Original
|
PDF
|
SN54GTL16622A,
SN74GTL16622A
18-BIT
SCBS673D
000-V
A114-A)
A115-A)
A115-A
C101
GTL16622A
SN54GTL16622A
SN74GTL16622A
|
A115-A
Abstract: C101 GTL16923 SN54GTL16923 SN74GTL16923
Text: SN54GTL16923, SN74GTL16923 18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVERS SCBS674E – AUGUST 1996 – REVISED NOVEMBER 1999 D D D D D D Members of the Texas Instruments Widebus Family D-Type Flip-Flops With Qualified Storage Enable Translate Between GTL/GTL+ Signal Levels
|
Original
|
PDF
|
SN54GTL16923,
SN74GTL16923
18-BIT
SCBS674E
000-V
A114-A)
A115-A)
A115-A
C101
GTL16923
SN54GTL16923
SN74GTL16923
|
Untitled
Abstract: No abstract text available
Text: SN74GTLPH16945 16-BIT LVTTL-TO-GTLP BUS TRANSCEIVER SCES292D – OCTOBER 1999 – REVISED NOVEMBER 2001 D D D D D D D D D D D D DGG OR DGV PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes
|
Original
|
PDF
|
SN74GTLPH16945
16-BIT
SCES292D
|
Untitled
Abstract: No abstract text available
Text: SN74GTLPH16945 16-BIT LVTTL-TO-GTLP BUS TRANSCEIVER SCES292C – OCTOBER 1999 – REVISED SEPTEMBER 2001 D D D D D D D D D D D D DGG, DGV, OR DL PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes
|
Original
|
PDF
|
SN74GTLPH16945
16-BIT
SCES292C
|
Untitled
Abstract: No abstract text available
Text: SN74GTLPH16945 16-BIT LVTTL-TO-GTLP BUS TRANSCEIVER SCES292B – OCTOBER 1999 – REVISED AUGUST 2001 D D D D D D D D D D DGG OR DGV PACKAGE TOP VIEW Member of Texas Instruments’ Widebus Family TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes
|
Original
|
PDF
|
SN74GTLPH16945
16-BIT
SCES292B
|
SN54GTL16622
Abstract: SN74GTL16622 SN74GTL16622DGGR
Text: SN54GTL16622, SN74GTL16622 18-BIT LVTTL-TO-GTL/GTL+ TRANSCEIVERS SCES049C – AUGUST 1995 – REVISED OCTOBER 1996 D D D D 1 64 2 63 3 62 4 61 5 60 6 59 7 58 8 57 9 56 10 55 11 54 12 53 13 52 14 51 15 50 16 49 17 48 18 47 19 46 20 45 21 44 22 43 23 42 24 41
|
Original
|
PDF
|
SN54GTL16622,
SN74GTL16622
18-BIT
SCES049C
SN54GTL16622
SN74GTL16622
SN74GTL16622DGGR
|
|
|
SN74GTLPH1645
Abstract: SN74GTLPH1645DGGR SN74GTLPH1645DGVR SN74GTLPH1645GQLR
Text: SN74GTLPH1645 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER SCES290A – OCTOBER 1999 – REVISED JANUARY 2001 D D D D D D D D D D DGG OR DGV PACKAGE TOP VIEW Member of Texas Instruments’ Widebus Family TI-OPC Circuitry Limits Ringing on
|
Original
|
PDF
|
SN74GTLPH1645
16-BIT
SCES290A
SN74GTLPH1645
SN74GTLPH1645DGGR
SN74GTLPH1645DGVR
SN74GTLPH1645GQLR
|
MPDS006C
Abstract: SN74GTLPH16945 SN74GTLPH16945GR SN74GTLPH16945KR SN74GTLPH16945VR
Text: SN74GTLPH16945 16-BIT LVTTL-TO-GTLP BUS TRANSCEIVER SCES292D – OCTOBER 1999 – REVISED NOVEMBER 2001 D D D D D D D D D D D D DGG OR DGV PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes
|
Original
|
PDF
|
SN74GTLPH16945
16-BIT
SCES292D
MPDS006C
SN74GTLPH16945
SN74GTLPH16945GR
SN74GTLPH16945KR
SN74GTLPH16945VR
|
Untitled
Abstract: No abstract text available
Text: SN54GTL16622, SN74GTL16622 18-BIT LVTTL-TO-GTL/GTL+ TRANSCEIVERS SCES049C – AUGUST 1995 – REVISED OCTOBER 1996 D D D D 1 64 2 63 3 62 4 61 5 60 6 59 7 58 8 57 9 56 10 55 11 54 12 53 13 52 14 51 15 50 16 49 17 48 18 47 19 46 20 45 21 44 22 43 23 42 24 41
|
Original
|
PDF
|
SN54GTL16622,
SN74GTL16622
18-BIT
SCES049C
SN54GTL16622
SN74GTL16622
|
Untitled
Abstract: No abstract text available
Text: SN74GTLPH1645 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER SCES290B – OCTOBER 1999 – REVISED AUGUST 2001 D D D D D D D D D D DGG OR DGV PACKAGE TOP VIEW Member of Texas Instruments’ Widebus Family TI-OPC Circuitry Limits Ringing on
|
Original
|
PDF
|
SN74GTLPH1645
16-BIT
SCES290B
|
5a2 zener diode
Abstract: ZENER 1B9 zener 5c2 zener DIODE 5c2 4c2 zener diode Zener Diode 1B9 2b9 zener diode 6c3 zener diode 4b2 zener diode RISCwatch 13h6422
Text: Application Note PowerPC Embedded Processors Design and Debug Considerations: PowerPC 750CX, 750CXe, and 750L Abstract - This application note discusses the use of certain reference designs and JTAG debugger probes with PowerPC 750CX/CXe processors and
|
Original
|
PDF
|
750CX,
750CXe,
750CX/CXe
PPC750
5a2 zener diode
ZENER 1B9
zener 5c2
zener DIODE 5c2
4c2 zener diode
Zener Diode 1B9
2b9 zener diode
6c3 zener diode
4b2 zener diode
RISCwatch 13h6422
|
Untitled
Abstract: No abstract text available
Text: SN74GTLPH1645 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER SCES290D – OCTOBER 1999 – REVISED SEPTEMBER 2001 D D D D D D D D D D D D DGG OR DGV PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family TI-OPC Circuitry Limits Ringing on
|
Original
|
PDF
|
SN74GTLPH1645
16-BIT
SCES290D
|
Untitled
Abstract: No abstract text available
Text: SN74GTLPH1645 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER SCES290C – OCTOBER 1999 – REVISED AUGUST 2001 D D D D D D D D D D DGG OR DGV PACKAGE TOP VIEW Member of Texas Instruments’ Widebus Family TI-OPC Circuitry Limits Ringing on
|
Original
|
PDF
|
SN74GTLPH1645
16-BIT
SCES290C
|
1B3GT
Abstract: 1b3 gt IC Tubes t448 1B3GT 7 pin T44B EIA 9-52 Scans-0017334 general electric
Text: 1B3-GT EM Cm O M CS 1B3-GT ET-T448D Page 1 DIODE 12-61 DESCRIPTION A N D RATING— - FOR TV HIGH-VOLTAGE RECTIFIER APPLICATIONS The 1B3-GT is a half-wave rectifier designed for use in high-voltage, low-current applications. It is especially suit able for use as the high-voltage rectifier in television receivers to supply power to the anode of television picture tubes.
|
OCR Scan
|
PDF
|
B8-58,
B6-60,
B5-82,
B6-144,
B7-166
1B3GT
1b3 gt
IC Tubes
t448
1B3GT 7 pin
T44B
EIA 9-52
Scans-0017334
general electric
|
BT153
Abstract: Thyristor TAG TI-1153 TAG thyristor TI1153 thyristor TAG 13 philips thyristor 239
Text: PHILIPS INTERNATIONAL SflE ]> • 711002t. 00S3Q35 301 * P H I N Bl 1b3 y v._ FAST TURN-OFF THYRISTOR Glass-passivated fast-turn-off thyristor in a T 0-220A B envelope, intended fo r use in inverter, pulse and switching applications. Its characteristics make the device extremely suitable fo r use in regulator,
|
OCR Scan
|
PDF
|
711002t.
00S3Q35
T0-220AB.
711Dfl2ti
BT153
7Z82059
BT153
Thyristor TAG
TI-1153
TAG thyristor
TI1153
thyristor TAG 13
philips thyristor 239
|
Untitled
Abstract: No abstract text available
Text: MACH 5 CPLD Family BEY O N D PER FO RM AN C E F ifth G e n e r a t i o n M A C H A r c h i t e l i . . ^ FEATURES P u b lic atio n # 2 0 4 4 6 A m e n d m e n t/0 Rev: G Issu e D ate: N o v e m b e r 1 9 9 8 MACH Families ♦ High logic densities and l/Os for increased logic integration
|
OCR Scan
|
PDF
|
LV-512/256-7AC-10AI.
M5LV-256/68
M5A3-256/68
|
