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    1993 SYNCHRONOUS DRAM JEDEC Search Results

    1993 SYNCHRONOUS DRAM JEDEC Result Highlights (6)

    Part ECAD Model Manufacturer Description Download Buy
    CS-USB2AMBMMC-001 Amphenol Cables on Demand Amphenol CS-USB2AMBMMC-001 Amphenol USB 2.0 High Speed Certified [480 Mbps] USB Type A to Micro B Cable - USB 2.0 Type A Male to Micro B Male [Android Sync + 28 AWG Fast Charge Ready] 1m (3.3') Datasheet
    CS-USB3IN1WHT-000 Amphenol Cables on Demand Amphenol CS-USB3IN1WHT-000 3-in-1 USB 2.0 Universal Apple/Android Charge & Sync Cable Adapter - USB Type A Male In - Apple Lightning (8-Pin) / Apple 30-Pin / USB Micro-B (Android) Male Out - White Datasheet
    CS-USB2AMBMMC-002 Amphenol Cables on Demand Amphenol CS-USB2AMBMMC-002 Amphenol USB 2.0 High Speed Certified [480 Mbps] USB Type A to Micro B Cable - USB 2.0 Type A Male to Micro B Male [Android Sync + 28 AWG Fast Charge Ready] 2m (6.6') Datasheet
    CDCV857ADGGR Texas Instruments 2.5V SSTL-II Phase Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications 48-TSSOP 0 to 85 Visit Texas Instruments
    CDCV857ADGGG4 Texas Instruments 2.5V SSTL-II Phase Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications 48-TSSOP 0 to 85 Visit Texas Instruments
    CDCV857ADGG Texas Instruments 2.5V SSTL-II Phase Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications 48-TSSOP 0 to 85 Visit Texas Instruments

    1993 SYNCHRONOUS DRAM JEDEC Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    TMS320AV110

    Abstract: AV110 TMS44400 1993 synchronous dram jedec SCSS013C tms320av11
    Text: TMS320AV110 MPEG AUDIO DECODER SCSS013C – MAY 1993 – REVISED AUGUST 1995 • • • • • • • Single-Chip ISO-MPEG Layers 1 and 2 Audio Decoder Decodes Mono, Dual, Stereo, and Joint Stereo Modes Supports All MPEG Sampling and Data Rates, Including Free Format


    Original     		PDF TMS320AV110 SCSS013C 15-Mbits/Second 18-Bit TMS320AV110 AV110 TMS44400 1993 synchronous dram jedec SCSS013C tms320av11

    TMS320AV110

    Abstract: tms320av11 tms320av pts 510 AV110 TMS44400 1993 synchronous dram jedec
    Text: TMS320AV110 MPEG AUDIO DECODER SCSS013C – MAY 1993 – REVISED AUGUST 1995 • • • • • • • Single-Chip ISO-MPEG Layers 1 and 2 Audio Decoder Decodes Mono, Dual, Stereo, and Joint Stereo Modes Supports All MPEG Sampling and Data Rates, Including Free Format


    Original     		PDF TMS320AV110 SCSS013C 15-Mbits/Second 18-Bit TMS320AV110 tms320av11 tms320av pts 510 AV110 TMS44400 1993 synchronous dram jedec

    1993 synchronous dram jedec

    Abstract: dram ddr 1997 1993 SDRAM
    Text: NEW PRODUCTS 3 128-Mbit DDR SYNCHRONOUS DRAM Yoshitomo Asakura Photo 1 µPD45128842 128Mbit DDR SDRAM NEC has newly developed a world-leading 128-Mb double data rate DDR synchronous DRAM (SDRAM) product (Photo 1) which comes in three configurations. Development Background


    Original     		PDF 128-Mbit PD45128842 128Mbit 128-Mb PD45D128442 Con36 1993 synchronous dram jedec dram ddr 1997 1993 SDRAM

    PROCESSOR

    Abstract: TMS34082 tms44c251 TMS44C251-10 TMS34020APCM40 TMS34010 TMS34020 74ALS373 equivalent transistor bc 102b SPVU019
    Text: TMS34020, TMS34020A GRAPHICS PROCESSORS SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993 • • • • • • • • • • • Instruction Cycle Time – 100 ns . . . TMS34020A-40 – 125 ns . . . TMS34020-32 – 125 ns . . . TMS34020A-32 Fully Programmable 32-Bit


    Original     		PDF TMS34020, TMS34020A SPVS004D TMS34020A-40 TMS34020-32 TMS34020A-32 32-Bit 512-Megabyte TMS34010 TMS34082 PROCESSOR tms44c251 TMS44C251-10 TMS34020APCM40 TMS34010 TMS34020 74ALS373 equivalent transistor bc 102b SPVU019

    TMS34082

    Abstract: TMS34010 SPVU019 TMS34020 TMS44C251
    Text: TMS34020, TMS34020A GRAPHICS PROCESSORS SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993 • • • • • • • • • • • Instruction Cycle Time – 100 ns . . . TMS34020A-40 – 125 ns . . . TMS34020-32 – 125 ns . . . TMS34020A-32 Fully Programmable 32-Bit


    Original     		PDF TMS34020, TMS34020A SPVS004D TMS34020A-40 TMS34020-32 TMS34020A-32 32-Bit 512-Megabyte TMS34010 TMS34082 TMS34010 SPVU019 TMS34020 TMS44C251

    XC3020L

    Abstract: XC3030L XC3042L XC3064L XC3090L XC7236A XC7318 KM48SL 1993 synchronous dram jedec XC7336TM
    Text: X-NOTES February 1995 The Programmable Logic Company SM Technical Marketing Series Number 3A Low Voltage Systems LOW VOLTAGE! MIXED VOLTAGE! 3 VOLTS! It's difficult to read the new product press without seeing similar words woven into the headlines. One could be led to believe that the


    Original     		PDF

    Untitled

    Abstract: No abstract text available
    Text: CDC2586 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS337C – FEBRUARY 1993 – REVISED OCTOBER 1998 D D D D D D Low Output Skew for Clock-Distribution and Clock-Generation Applications Operates at 3.3-V VCC Distributes One Clock Input to Twelve


    Original     		PDF CDC2586 SCAS337C SCAA033A CDC2586PAH CDC2586PAHR

    Untitled

    Abstract: No abstract text available
    Text: CDC586 3.3-V PHASE-LOCK-LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS336D – FEBRUARY 1993 – REVISED OCTOBER 1998 D D D D D D Low Output Skew for Clock-Distribution and Clock-Generation Applications Operates at 3.3-V VCC Distributes One Clock Input to Twelve


    Original     		PDF CDC586 SCAS336D SDYA012 SCAA033A SCAA029, CDC586PAH CDC586PAHR

    Untitled

    Abstract: No abstract text available
    Text: CDC2586 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS337C – FEBRUARY 1993 – REVISED OCTOBER 1998 D D D D D D Low Output Skew for Clock-Distribution and Clock-Generation Applications Operates at 3.3-V VCC Distributes One Clock Input to Twelve


    Original     		PDF CDC2586 SCAS337C CDC2586PAH CDC2586PAHR SCAA028 SSYA008 SCAA033A SZZA017A

    Untitled

    Abstract: No abstract text available
    Text: CDC586 3.3-V PHASE-LOCK-LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS336D – FEBRUARY 1993 – REVISED OCTOBER 1998 D D D D D D Low Output Skew for Clock-Distribution and Clock-Generation Applications Operates at 3.3-V VCC Distributes One Clock Input to Twelve


    Original     		PDF CDC586 SCAS336D SCBA006A SCBA004C SDYA010 SDYA012 SCAA033A SZZA017A SCAA029,

    siplace 80 f4

    Abstract: siplace chrysler ic chrysler Siemens Smart Power IC
    Text: Spectrum Semiconductor Group Ambitious goals for the turn of the century Despite deteriorating prices and a weakening market, the Siemens Semiconductor Group can look back on a successful 1995/96 fiscal year, with new orders at DM 4.8 billion, sales of DM 4.7 billion and profits of


    Original     		PDF

    Mitsubishi transistor C 1588

    Abstract: MH64D72KLH-10 MH64D72KLH-75 dram memory module 1993
    Text: Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH64D72KLH-75,-10 4,831,838,208-BIT 67,108,864-WORD BY 72-BIT Double Data Rate Synchronous DRAM Module DESCRIPTION The MH64D72KLH is 67108864 - word x 72-bit Double Data Rate(DDR) Sy nchronous DRAM mounted module.


    Original     		PDF MH64D72KLH-75 208-BIT 864-WORD 72-BIT) MH64D72KLH 72-bit 133MHz. 93pin 144pin 52pin Mitsubishi transistor C 1588 MH64D72KLH-10 dram memory module 1993

    CDC2586

    Abstract: MS-026
    Text: CDC2586 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS337C – FEBRUARY 1993 – REVISED OCTOBER 1998 D D D D D D Low Output Skew for Clock-Distribution and Clock-Generation Applications Operates at 3.3-V VCC Distributes One Clock Input to Twelve


    Original     		PDF CDC2586 SCAS337C CDC2586 MS-026

    CDC586

    Abstract: MS-026 SCAS336D
    Text: CDC586 3.3-V PHASE-LOCK-LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS336D – FEBRUARY 1993 – REVISED OCTOBER 1998 D D D D D D Low Output Skew for Clock-Distribution and Clock-Generation Applications Operates at 3.3-V VCC Distributes One Clock Input to Twelve


    Original     		PDF CDC586 SCAS336D CDC586 MS-026 SCAS336D

    pjuaa

    Abstract: 1993 SDRAM 7216B
    Text: 16 777 216 BIT SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY S M 0 S6 82-J A N U A R Y 1993 DGE PACKAG ET TOP VIEW Organization. . . 1M x 8 x 2 Banks 3.3 V-Power Supply (10% Tolerance) Two Banks For On-Chip Interleaving (Gapless Accesses) * High Bandwidth - Up to 100-MHz Data


    OCR Scan     		PDF 40must pin35must SDRAM-15 pjuaa 1993 SDRAM 7216B

    266DR

    Abstract: No abstract text available
    Text: TMS320AV110 MPEG AUDIO DECODER SCSS013C - MAY 1993 - REVISED AUGUST 1995 • Single-Chip ISO-MPEG Layers 1 and 2 Audio Decoder • 16- or 18-Bit Serial PCM Output Directly Interfaces to Most Serial D/A Converters • Decodes Mono, Dual, Stereo, and Joint


    OCR Scan     		PDF TMS320AV110 SCSS013C 15-Mbits/Second 18-Bit G1021S3 S-PQFP-G120) MS-022 266DR

    MT48LC2M8S1

    Abstract: 1993 synchronous dram jedec A221D 1993 SDRAM
    Text: ADVANCE M T48LC2M 8S1 2 MEG X 8 SDRAM p ilC R O N 3.3 VOLT, PULSED RAS, DUAL BANK, SELF REFRESH FEATURES PIN ASSIGNMENT Top View • Fully synchronous; all signals (excluding clock enable) registered to positive edge of system clock • Dual 1 Meg x 8s, separate, internal banks controlled by A ll


    OCR Scan     		PDF T48LC2M 096-cycle MT48LC2M8S1 1993 synchronous dram jedec A221D 1993 SDRAM

    266DR

    Abstract: No abstract text available
    Text: TMS320AV110 MPEG AUDIO D E C O D E R S C S S 01 3C -M A Y 1 9 9 3 - REVISED AUGUST 1995 * S i ng l e - C h i p I S O - M P E G L a y e r s 1 and 2 A ud i o D e c o d e r * 1 6 - or 1 8-Bit Serial P C M O u t p u t Direct ly I nt e r f a c e s to M o s t Serial D/ A C o n v e r t e r s


    OCR Scan     		PDF TMS320AV110 266DR

    A9281

    Abstract: 1993 SDRAM ra2t 1993 SDRAM samsung KM48SV2000
    Text: PRELIMINARY CMOS SDRAM KM48SV2000 2M X 8 BIT SYNCHRONOUS DYNAMIC RAM GENERAL DESCRIPTION FEATURES The KM48SV2000 is a 16,777,216 bit synch­ ronous high data rate Dynamic RAM organized as 2,097,152 words by 8bits, fabricated with SAMSUNG'S high performance CMOS technology.


    OCR Scan     		PDF KM48SV2000 KM48SV2000 17SMAX -16ELECTRONICS A9281 1993 SDRAM ra2t 1993 SDRAM samsung

    8207 intel

    Abstract: interfacing intel 8086 with ram and rom difference between intel 80186 and intel 80286 pro difference between intel 8086 and intel 80186 pro lt 8207 8207 PEB 2426 ROA20 i8207 iAPX 88 all register
    Text: 8207 DUAL-PORT DYNAMIC RAM CONTROLLER • P rovides All Signais Necessary to Control 16K, 64K and 256K Dynamic RAMs ■ D irectly A ddresses and Drives up to 2 M egabytes w ithout External Drivers ■ Supports Single and Dual-Port Configurations ■ A utom atic RAM Initialization in All


    OCR Scan     		PDF --T36 L-T35 --T34 --T26 5TCLCL--T34 5TCLCL--T36 8207 intel interfacing intel 8086 with ram and rom difference between intel 80186 and intel 80286 pro difference between intel 8086 and intel 80186 pro lt 8207 8207 PEB 2426 ROA20 i8207 iAPX 88 all register

    Untitled

    Abstract: No abstract text available
    Text: TMS34020, TMS34020A GRAPHICS PROCESSORS SPVS004D - MARCH 1990 - REVISED NOVEMBER 1993 * Instruction Cycle Time - 100 ns . . . TMS34020A-40 - 1 2 5 n s . . .TMS34020-32 - 125 n s . . . TMS34020A-32 145-PIN GB PACKAGE TOP VIEW A B C D E F G H J • Fully Programmable 32-Bit


    OCR Scan     		PDF TMS34020, TMS34020A SPVS004D TMS34020A-40 TMS34020-32 TMS34020A-32 145-PIN 5bl72E

    PEEL programming

    Abstract: 22CV10Z-25 22CV10 22CV10A-10 PEEL22CV10 22CV10A PEEL 22CV10A-15 22CV10A-7 22GV10
    Text: PEEL 22GV10 Z A M SEMICONDUCTORS CMOS Programmable Electrically Erasable Logic Device i February 1993 Features General Description Advanced CMOS EEPROM Technology High Performance with Low Power Consumption The AMI PEEL22C V10(Z) is a CMOS Program m able


    OCR Scan     		PDF 22CV10 PEEL programming 22CV10Z-25 22CV10A-10 PEEL22CV10 22CV10A PEEL 22CV10A-15 22CV10A-7 22GV10

    TMS34082

    Abstract: No abstract text available
    Text: T M S 34020, T M S 3 4 0 2 0 A GRAPHICS PROCESSORS SPVS004D - MARCH 1990 - REVISED NOVEMBER 1993 * * * 1115-PIN GB PACKAGE TOP VIEW Instruction C y cle Tim e - 100 ns . . . T M S 3 4 0 2 0 A - 4 0 - 125 ns . . . T M S 3 4 0 2 0 - 3 2 - 125 ns . . . T M S 3 4 0 2 0 A - 3 2


    OCR Scan     		PDF SPVS004D 15-PIN 32-Bit TMS34082

    "Lookaside Cache"

    Abstract: No abstract text available
    Text: / T T SCS-THOMSON TA125 TECHNICAL ARTICLE Synchronous Burst SRAM for secondary CACHE systems Ricky Tuttle SGS-THOMSON Microelectronics Carrollton, USA The advent of high speed microprocessors and the requirement for high performance systems has opened the door to the Fast SRAM FSRAM mar­


    OCR Scan     		PDF TA125 486TM MK62486, MK62940 32-bit 64-bit MK62486 "Lookaside Cache"