smd transistor w16
Abstract: transistor smd w16 PALC22V10B-15DMB 256K x 8 SRAM CY7C128A SRAM PALC22V10B-20DMB Mil JAN jm38510 Cross Reference smd cross reference smd w20 CY7C245-45WMB 455b
Text: SMD Cross Reference Listed below are the SMDs for which Cypress is an approved source of supply. Please contact your local Cypress representative or see the Cypress website www.cypress.com for the latest SMD update. All part numbers that have an X in the PPL (Preferred
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CY6116A-35DMB
CY6116A-35LMB
840ER
Pre-1985
smd transistor w16
transistor smd w16
PALC22V10B-15DMB
256K x 8 SRAM CY7C128A SRAM
PALC22V10B-20DMB
Mil JAN jm38510 Cross Reference
smd cross reference
smd w20
CY7C245-45WMB
455b
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Untitled
Abstract: No abstract text available
Text: fax id: 6150 PRELIMINARY Ultra37192 UltraLogic 192-Macrocell ISR™ CPLD Features • • • • • • • • • • • 192 macrocells in twelve logic blocks • In-System Reprogrammable ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes
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Ultra37192
192-Macrocell
IEEE1149
160-pin
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tlp 453
Abstract: No abstract text available
Text: fax id: 6151 PRELIMINARY Ultra37192V UltraLogic 3.3V 192-Macrocell ISR™ CPLD — tPD = 10 ns Features — tS = 5.5 ns • 192 macrocells in twelve logic blocks • IEEE standard 3.3V operation — 3.3V ISR • • • • • • • • • — 5V tolerant
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Ultra37192V
192-Macrocell
IEEE1149
tlp 453
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c341 transistor
Abstract: 7C341 diode c341 CY7C341 84-PIN C341
Text: 41 CY7C341 192-Macrocell MAX EPLD Features • • • • • • 192 macrocells in 12 LABs 8 dedicated inputs, 64 bidirectional I/O pin 0.8-micron double-metal CMOS EPROM technology Programmable interconnect array 384 expander product terms Available in 84-pin HLCC, PLCC, and PGA packages
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CY7C341
192-Macrocell
84-pin
CY7C341
c341 transistor
7C341
diode c341
C341
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VHDL code for pci
Abstract: No abstract text available
Text: Press Release CYPRESS OFFERS FIRST PCI CORES FOR CPLDs Free Cores Provided as VHDL Source Code for Easy Integration into Ultra37000 CPLDs SAN JOSE, Calif., January 25, 1999 Cypress Semiconductor Corporation today introduced the first PCI cores designed specifically for CPLDs. The new PCI cores, exclusively for use with the Ultra37000 family of CPLDs, are
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Ultra37000
32-bit,
33-MHz
Ultra37000,
VHDL code for pci
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8 bit multiplier using vhdl code
Abstract: ado1 "Single-Port RAM"
Text: Designing ispLSI 6000 Devices in the Synplicity Environment ® 2. c4r4pl: four counters up/down, 8/16 bits, parallel load are configured as a 16-bit counter, default is up. Counter sizes can be independently changed to 8 or 16 bits for each bank; default is 16-bit. Once up, down
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16-bit
16-bit.
1-800-LATTICE.
8 bit multiplier using vhdl code
ado1
"Single-Port RAM"
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vhdl code for parallel to serial shift register
Abstract: isplsi architecture
Text: Designing ispLSI 6000 Devices in the Synplicity Environment ® 2. c4r4pl: four counters up/down, 8/16 bits, parallel load are configured as a 16-bit counter, default is up. Counter sizes can be independently changed to 8 or 16 bits for each bank; default is 16-bit. Once up, down
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16-bit
16-bit.
1-800-LATTICE.
vhdl code for parallel to serial shift register
isplsi architecture
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CY37192
Abstract: CY37192V ultraISR CABLE
Text: 7192 Back CY37192 UltraLogic 192-Macrocell ISR™ CPLD Features • • • • • • • • • • • 192 macrocells in twelve logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes
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CY37192
192-Macrocell
160-pin
CY37192
CY37192V
ultraISR CABLE
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vhdl code for dice game
Abstract: Video Proc 3.3V 0.07A 64-Pin PQFP ez811 GRAPHICAL LCD interfaced with psoc 5 cypress ez-usb AN2131QC CYM9239 vhdl code PN 250 code generator CY3649 cy7c63723 Keyboard and Optical mouse program CY7C9689 ethernet
Text: Product Selector Guide Communications Products Description Pins Part Number Freq. Range Mbps ICC (mA) Packages* 3.3V SONET/SDH PMD Transceiver 2.5V SiGe Low Power SONET/SDH Transceiver SONET/SDH Transceiver w/ 100K Logic 2.5 G-Link w/ 100K Logic OC-48 Packet Over SONET (POS) Framer
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OC-48
CYS25G0101DX
CYS25G0102
CYS25G01K100
CYP25G01K100
CY7C9536
CY7C955
CY7B952
CY7B951
10BASE
vhdl code for dice game
Video Proc 3.3V 0.07A 64-Pin PQFP
ez811
GRAPHICAL LCD interfaced with psoc 5
cypress ez-usb AN2131QC
CYM9239
vhdl code PN 250 code generator
CY3649
cy7c63723 Keyboard and Optical mouse program
CY7C9689 ethernet
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341B
Abstract: 84-PIN CY7C341B
Text: 341B CY7C341B 192-Macrocell MAX EPLD Features Typical ICC vs. fMAX • 192 macrocells in 12 LABs • 8 dedicated inputs, 64 bidirectional I/O pin • Advanced 0.65-micron CMOS technology to increase performance • Programmable interconnect array • 384 expander product terms
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CY7C341B
192-Macrocell
65-micron
84-pin
CY7C341B
341B
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D168K
Abstract: PALC22V10B-20DMB CY7C186A-20DMB CY7C109L CY7C408A-15DMB CY7C342B-25RMB palc22v10b20dmb PALCE22V10-30DMB PALC22V10-30DMB CY6116A35LMBSMD
Text: SMD Cross Reference Listed below are the SMDs for which Cypress is an approved source of supply. Please contact your local Cypress representative or see the Cypress website www.cypress.com for the latest SMD update. All part numbers that have a date in the PPL (Preferred
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CY7C128A-45DMB
CY6116A-55DMB
L-PRF-38535
Pre-1985
D168K
PALC22V10B-20DMB
CY7C186A-20DMB
CY7C109L
CY7C408A-15DMB
CY7C342B-25RMB
palc22v10b20dmb
PALCE22V10-30DMB
PALC22V10-30DMB
CY6116A35LMBSMD
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84-PIN
Abstract: CY7C341B
Text: CY7C341B y CYPRESS Features • 192 macrocells in 12 LABs • 8 dedicated inputs, 64 bidirectional I/O pin • Advanced 0.65-micron CMOS technology to increase performance • Programmable interconnect array • 384 expander product terms • Available in 84-pin HLCC, PLCC, and
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CY7C341B
65-micron
84-pin
CY7C341B
CY7C341Bis
35RC/RI
84-Lead
CY7C341Bâ
35HMB
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Untitled
Abstract: No abstract text available
Text: PRELIMINARY CY37192V UltraLogic 3.3V 192-Macrocell ISR™ CPLD — tPD = 12 ns Features — ts = 7 n s • 192 macrocells in twelve logic blocks • IEEE standard 3.3V operation — tco = 6.5 ns Product-term clocking IEEE 1149.1 JTAG boundary scan Programmable slew rate control on individual l/Os
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CY37192V
192-Macrocell
160-pin
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Untitled
Abstract: No abstract text available
Text: PRELIMINARY Cr CY37192 UltraLogic 192-Macrocell ISR™ CPLD — tco = 4.5 ns Features • 192 macrocells in twelve logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes
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CY37192
192-Macrocell
160-pin
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Untitled
Abstract: No abstract text available
Text: Ultra37192V UltraLogic 3.3V 192-Macrocell ISR™ CPLD Features — tpD = 12 ns — ts = 7 ns • 192 macrocells in twelve logic blocks • IEEE standard 3.3V operation — tco = 6 .5 ns • Product-term clocking — 3.3V ISR • IEEE1149.1 JTAG boundary scan
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Ultra37192V
192-Macrocell
IEEE1149
16ctor
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c3415
Abstract: cy7c341-30jc CY7C341
Text: CY7C341 y CYPRESS Features • • • • • • 192 macrocells in 12 LABs 8 dedicated inputs, 64 bidirectional I/O pin 0.8-micron double-metal CMOS EPROM technology Programmable interconnect array 384 expander product terms Available in 84-pin HLCC, PLCC, and PGA packages
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CY7C341
192-Macrocell
84-pin
CY7C341
c3415
cy7c341-30jc
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EPM5130
Abstract: EPM5016
Text: E P M 5016 to E P M 5192 E PLD s High-Speed, High-Density MAX 5000 Devices Data Sheet September 1991, ver. 2 Features □ □ □ □ □ □ Complete family of CMOS EPLDs solves design tasks ranging from fast 20-pin address decoders to 100-pin LSI custom peripherals.
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20-pin
100-pin
15-ns
EPM5130
EPM5016
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programming manual EPLD EPS448
Abstract: Altera EPM5128 EPM7064-12 leap u1 EP-900910 PLE3-12a tcl tv circuit altera eplds EP610 "pin compatible" ALTERA MAX 5000
Text: Data Book TENTH ANNIVERSARY A Decade of Leadership A u g u s t 1993 Data Book August 1993 A-DB-0793-01 Altera, MAX, and M A X+PLUS are registered trademarks of Altera Corporation. The following, among others, are trademarks of Altera Corporation: AHDL, M AX+PLUS II, PL-ASAP2, PLDS-HPS, PLS-ADV, PLS-ES, PLS-FLEX8, PLS-FLEX8/H P, PLS-FLEX8/SN , PLS-HPS, PLS-STD, PLS-W S/H P,
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-DB-0793-01
EP330,
EP610,
EP610A,
EP610T,
EP910,
EP910A,
EP910T,
EP1810,
EP1810T,
programming manual EPLD EPS448
Altera EPM5128
EPM7064-12
leap u1
EP-900910
PLE3-12a
tcl tv circuit
altera eplds
EP610 "pin compatible"
ALTERA MAX 5000
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wl1251
Abstract: 464X1
Text: CY7C341 PRELIMINARY r CYPRESS SEMICONDUCTOR 192-Macrocell MAX EPLD Features Logic A rray Blocks • 192 macrocells in 12 LABa T h e re are 12 logic array blocks in the CY7C341. Each LAB consists o f a m acro cell array containing 16 m acrocells, an ex
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CY7C341
192-Macrocell
CY7C341
84-pin
ithi7C341
--35R
--40R
wl1251
464X1
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Altera EPM5128
Abstract: WKX 62 EPM5016 epm5130 pinouts for 7400 series EPM5064 EPM5192 program EPM5032 EPM5128 PACKAGING PLDS-MAX
Text: EPM5016 to EPM5192 EPLDs High-Speed, High-Density MAX 5000 Devices Data Sheet September 1991, ver. 2 Features □ □ □ □ □ □ Complete family of CMOS EPLDs solves design tasks ranging from fast 20-pin address decoders to 100-pin LSI custom peripherals.
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EPM5016
EPM5192
20-pin
100-pin
15-ns
Altera EPM5128
WKX 62
epm5130
pinouts for 7400 series
EPM5064
program EPM5032
EPM5128 PACKAGING
PLDS-MAX
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pin configuration IC 74151
Abstract: IC 74151 diagram and truth table IC TTL 7400 diagram and truth table ic 74151 full adder using Multiplexer IC 74151 Multiplexer IC 74151 programmer manual EPLD cypress IC 7400 SERIES ALL DATA programming manual EPLD cy7c342
Text: CYPRESS SEMICONDUCTOR HOE D 256*^2 DD05427 5 ICYP 7 T V d -/3 -4 7 CY7C340 EPLD Family « 1 ^ CYPRESS SEMICONDUCTOR Multiple Array Matrix High-Density EPLDs Features General Description • Erasable, user-configurable CMOS EPLDs capable of implementing high-density custom logic functions
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CY7C340
CY7C344-25WC/WI
CY7C344-25HC/HI
CY7C344-25JC/JI
CY7C344-25HMB
CY7C344-25WMB
CY7C344-25DMB
CY7C344-35HMB
CY7C344-35WMB
CY7C344-35DMB
pin configuration IC 74151
IC 74151 diagram and truth table
IC TTL 7400 diagram and truth table
ic 74151
full adder using Multiplexer IC 74151
Multiplexer IC 74151
programmer manual EPLD cypress
IC 7400 SERIES ALL DATA
programming manual EPLD
cy7c342
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Untitled
Abstract: No abstract text available
Text: CY37192 UltraLogic 192-Macrocell ISR™ CPLD Features — tco = 4 .5 ns • Product-term clocking • 192 macrocells in twelve logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming — Design changes d on’t cause pinout changes
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CY37192
192-Macrocell
160-pin
CY37192V,
Y37128/37128V,
CY372n
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Untitled
Abstract: No abstract text available
Text: fax id: 6150 CYPRESS PRELIMINARY Ultra37192 UltraLogic 192-Macrocell ISR™ CPLD Product-term clocking IEEE1149.1 JTAG boundary scan Programmable slew rate control on individual l/Os Low power option on individual logic block basis 5V and 3.3V I/O capability
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Ultra37192
192-Macrocell
IEEE1149
160-pin
Ultra37256
Ultra37128
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Untitled
Abstract: No abstract text available
Text: '0 CYPRESS Features • 192 m acrocells in 12 L A B s • 8 dedicated inputs, 64 bidirectional I/O pin • Advanced 0.65-micron CMOS technology to increase performance • Programmable interconnect array • 384 expander product terms • Available in 84-pin HLCC, PLCC, and
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CY7C341B
65-micron
84-pin
CY7C341B
16perLAB.
prodB-30HMB
84-Lead
001b741
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