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    16RP4 Price and Stock

    Vishay Sfernice P16RP472MAB15

    POT 4.7K OHM 1W CERMET LINEAR
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    DigiKey P16RP472MAB15 Box 35 1
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    Vishay Sfernice P16RP473MAB15

    POT 47K OHM 1W CERMET LINEAR
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    DigiKey P16RP473MAB15 Box 33 1
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    Vishay Sfernice P16RP471KAB15

    P16 RP 470U 10% A BO E3
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    DigiKey P16RP471KAB15 Bulk 20
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    Vishay Sfernice P16RP470KAB15

    P16 RP 47U 10% A BO E3
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    Vishay Sfernice P16RP470MAB15

    P16 RP 47U 20% A BO E3
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    DigiKey P16RP470MAB15 Bulk 20
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    16RP4 Datasheets (4)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    16RP4ADC Nihon Inter Electronics Programmable Logic Array Scan PDF
    16RP4ADCQR Nihon Inter Electronics Programmable Logic Array Scan PDF
    16RP4APC Nihon Inter Electronics Programmable Logic Array Scan PDF
    16RP4APCQR Nihon Inter Electronics Programmable Logic Array Scan PDF

    16RP4 Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    16V8

    Abstract: GAL16LV8 GAL16LV8C GAL16LV8C-10LJ GAL16LV8C-15LJ GAL16LV8C-7LJ GAL16LV8D GAL16LV8D-3LJ GAL16LV8D-5LJ
    Text: ree Lead-Fage P a c k ns Optio le! b Availa Features GAL16LV8 Low Voltage E2CMOS PLD Generic Array Logic Functional Block Diagram • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 3.5 ns Maximum Propagation Delay — Fmax = 250 MHz — 2.5 ns Maximum from Clock Input to Data Output


    Original
    GAL16LV8 GAL16LV8C) 16V8 GAL16LV8 GAL16LV8C GAL16LV8C-10LJ GAL16LV8C-15LJ GAL16LV8C-7LJ GAL16LV8D GAL16LV8D-3LJ GAL16LV8D-5LJ PDF

    GAL16V8Z

    Abstract: GAL16V8Z-12QJ GAL16V8Z-12QP GAL16V8Z-12QS GAL16V8Z-15QJ GAL16V8Z-15QP GAL16V8Z-15QS GAL16V8ZD-12QJ GAL16V8ZD-12QP
    Text: GAL 16V8Z/GAL16V8ZD Device Datasheet June 2010 All Devices Discontinued! Product Change Notifications PCNs have been issued to discontinue all devices in this data sheet. The original datasheet pages have not been modified and do not reflect those changes.


    Original
    16V8Z/GAL16V8ZD GAL16V8Z GAL16V8ZD GAL16V8Z-12QS GAL16V8Z-15QS GAL16V8Z-12QJ GAL16V8Z-12QP GAL16V8Z-15QJ GAL16V8Z-15QP GAL16V8ZD-12QJ GAL16V8Z GAL16V8Z-12QJ GAL16V8Z-12QP GAL16V8Z-12QS GAL16V8Z-15QJ GAL16V8Z-15QP GAL16V8Z-15QS GAL16V8ZD-12QJ GAL16V8ZD-12QP PDF

    16R8

    Abstract: GAL16LV8ZD GAL16LV8ZD-15QJ GAL16LV8ZD-25QJ GAL16V8
    Text: Specifications GAL16LV8ZD GAL16LV8ZD Low Voltage, Zero Power E2CMOS PLD Generic Array Logic FUNCTIONAL BLOCK DIAGRAM FEATURES • 3.3V LOW VOLTAGE, ZERO POWER OPERATION — JEDEC Compatible 3.3V Interface Standard — Interfaces with Standard 5V TTL Devices


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    GAL16LV8ZD 16R8 GAL16LV8ZD GAL16LV8ZD-15QJ GAL16LV8ZD-25QJ GAL16V8 PDF

    7486 XOR GATE

    Abstract: circuit diagram of half adder using IC 7486 7486 2-input xor gate ic 7486 XOR GATE pin configuration IC 7486 pin configuration of 7486 IC vhdl code for vending machine pin DIAGRAM OF IC 7486 data sheet IC 7408 laf 0001
    Text: Lattice Semiconductor Handbook 1994 Click on one of the following choices: • Table of Contents • How to Use This Handbook • Go to Main Menu 1996 Lattice Semiconductor Corporation. All rights reserved. Lattice Semiconductor Handbook 1994 i Copyright © 1994 Lattice Semiconductor Corporation.


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    PDF

    PLSI 1016-60LJ

    Abstract: PAL 007 pioneer pal16r8 programming algorithm PAL 008 pioneer lattice 1016-60LJ ISP Engineering Kit - Model 100 PLSI-2064-80LJ GAL16v8 programmer schematic GAL programming Guide ispLSI 2064-80LT
    Text: Lattice Semiconductor Data Book 1996 Click on one of the following choices: • Table of Contents • Data Book Updates & New Products • Go to Main Menu 1996 Lattice Semiconductor Corporation. All rights reserved. ispLSI and pLSI Product Index Pins Density


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    1016E 1032E 20ters 48-Pin 304-Pin PLSI 1016-60LJ PAL 007 pioneer pal16r8 programming algorithm PAL 008 pioneer lattice 1016-60LJ ISP Engineering Kit - Model 100 PLSI-2064-80LJ GAL16v8 programmer schematic GAL programming Guide ispLSI 2064-80LT PDF

    16l8 JEDEC fuse

    Abstract: 16R8 GAL16LV8ZD GAL16LV8ZD-15QJ GAL16LV8ZD-25QJ GAL16V8 XOR-2055 ac1212
    Text: GAL16LV8ZD Low Voltage, Zero Power E2CMOS PLD Generic Array Logic Features Functional Block Diagram • 3.3V LOW VOLTAGE, ZERO POWER OPERATION — JEDEC Compatible 3.3V Interface Standard — Interfaces with Standard 5V TTL Devices — 50µA Typical Standby Current 100µA Max.


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    GAL16LV8ZD 16l8 JEDEC fuse 16R8 GAL16LV8ZD GAL16LV8ZD-15QJ GAL16LV8ZD-25QJ GAL16V8 XOR-2055 ac1212 PDF

    GAL16V8

    Abstract: IC gal16v8 gal16v8b-10lj 16v8b GAL programmer schematic gal16v8 programming 16V8 GAL16V8B-7LJ GAL16V8B-7LP GAL16V8C
    Text: Specifications GAL16V8 GAL16V8 High Performance E2CMOS PLD Generic Array Logic FUNCTIONAL BLOCK DIAGRAM FEATURES 2 • HIGH PERFORMANCE E CMOS TECHNOLOGY — 5 ns Maximum Propagation Delay — Fmax = 166 MHz — 4 ns Maximum from Clock Input to Data Output


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    GAL16V8 GAL16V8 IC gal16v8 gal16v8b-10lj 16v8b GAL programmer schematic gal16v8 programming 16V8 GAL16V8B-7LJ GAL16V8B-7LP GAL16V8C PDF

    PICTURE TUBE

    Abstract: cathode ray cathode ray tube Scans-0017308
    Text: TENTATIVE DATA , I6 R P 4 - TUNG-SOL N CATHODE RAY COATED UNIPOTENTIAL CATHODE HEATER 6 .3 VO LTS 0.6 AMP. AC OR DC R ECT ANG UL AR GLASS SMALL TH E 16RP4 PICTURE FOR A IS TUBE AN ALL FOR PICTURE GUN D ES IG N ED ION-SPOT FO R IN CREASED


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    16RP4 PICTURE TUBE cathode ray cathode ray tube Scans-0017308 PDF

    111J

    Abstract: 16A4 16RP4A 16X4 PAL16RA8
    Text: 20-Pin PAL/HAIL Devices 16P8A 16RP6A 16RP4A 16RA8 P L ^ _ > ° J 20] VCC T io |T HA CELL — 11^ RA CELL — a lt RA CELL I3 ^ RA CELL » Jo o i]]o 2 — j j ] 03 Tb] o 4 14^ RA CELL — IsQT RA CELL - ] 3 ° 5 I6 ^ [ RA CELL - u 06 17 ^ RA CELL


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    20-Pin 16P8A 16RP8A 16RP6A 16RP4A 16RA8 16R4/B/B-2/B-4 111J 16A4 16RP4A 16X4 PAL16RA8 PDF

    Untitled

    Abstract: No abstract text available
    Text: PAL/H AL Devices Logic Diagram 16RP4 0 12 3 4 5 6 7 0 0 10 11 12131415 1617 IB IS 2021 2223 24 252627 28 293031 ip p o t>°- _ iP ^ =*3— 1P 9I>H D > Q p p '9 E>^ O Q > Q D Q > Q = * J- = * J - I P i p -h = H>= * h ip -p E > fi D Q > Q = * h S > 3D —►


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    16RP4 PDF

    16RP4A

    Abstract: 200S PAL16RP4A PAL16RP6A PAL16RP8A 16P8A
    Text: Medium 20PA Series 16P8A, 16RP8A, 16RP6A, 16RP4A Medium 20PA Series O UTPUTS C O M B IN A T O R IA L R E G IS T E R E D tpD* ns •cc <mA) 8 6 4 8 2 4 2 5 /3 0 2 5 /3 0 2 5 /3 0 2 5 /3 0 180 180 180 180 A R R A Y IN P U T S PA LI 6P8A PAL16RP8A PAL16RP6A


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    16P8A, 16RP8A, 16RP6A, 16RP4A PAL16RP8A PAL16RP6A PAL16RP4A 16RP4A 200S 16P8A PDF

    Untitled

    Abstract: No abstract text available
    Text: 16P8B, 16RP8B, 16RP6B, 16RP4B Programmable Logic Array F A IR C H IL D A Schlumberger Company Description Connection Diagram The FASTPLA 16P8B Series of h ig h -p e rfo rm a n c e b ip o la r progra m m a ble logic arrays provide 15 ns m axim um p ropag ation delays and are fu lly c o m p a tib le w ith in d u stry


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    16P8B, 16RP8B, 16RP6B, 16RP4B 16P8B 20-pin 16PR6B, PDF

    Untitled

    Abstract: No abstract text available
    Text: Medium 2 0P A Series 16P8A, 16RP8A, 16RP6A, 16RP4A Medium 20PA Series OUTPUTS *PD* AR R AY INPUTS PAL16P8A PAL16RP8A PAL16RP6A 16RP4A COMBINATORIAL REGISTERED 8 6 4 8 2 4 16 16 16 16 •cc ns (mA) 2 5 /3 0 2 5 /3 0 2 5 /3 0 2 5 /3 0 180 180 180 180 * 2 5 n s a ctiv e low, 3 0 n s activ e high


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    16P8A, 16RP8A, 16RP6A, 16RP4A PAL16P8A PAL16RP8A PAL16RP6A PAL16RP4A 16RP6A 242S2S27 PDF

    16P8B

    Abstract: 16H8
    Text: 16P8B, 16RP8B, 16RP6B, 16RP4B Programmable Logic Array F A IR C H IL D A S ch lu m b e rg e r C o m p a n y Description Connection Diagram T h e F A S T P L A 16P 8B S e rie s o f h ig h - p e r fo rm a n c e b ip o la r p ro g ra m m a b le lo g ic a rra y s p ro v id e 15 ns m a x im u m


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    16P8B, 16RP8B, 16RP6B, 16RP4B 16P8B 20-pin 16PR6B, 16H8 PDF

    t1146

    Abstract: 1038i Scans-0017308
    Text: 16KP4-A/16RP4-A ET-T1146A 16K P 4-A /16R P 4-A g ù ê iï* Page 1 7-56 CATHODE-RAY TUBE TUBES 16-INCH RECTANGULAR, GLASS 13’/ 2- BY IO'/s-INCH PICTURE SIZE FOCUS— MAGNETIC FACEPLATE— SPHERICAL, GRAY DEFLECTION— MAGNETIC ION-TRAP GUN 70-DEGREE DEFLECTION ANGLE


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    16KP4-A/16RP4-A 16-INCH 70-DEGREE 16KP4-A/16RP4-A ji-21 b5-57 t1146 1038i Scans-0017308 PDF

    Untitled

    Abstract: No abstract text available
    Text: o / é + .„ Ô FA IR C H ILD es I o c A S c h lu m b e rg e r Co m p a n y 4 16P8A, 16RP8A, 16RP6A, 16RP4A Programmable Logic Array September 1986 PRELIMINARY INFORMATION M e m o r y & H i g h S p e e d L o g ic D e s c r ip tio n C o n n e c t io n D ia g r a m


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    16P8A, 16RP8A, 16RP6A, 16RP4A PDF

    16A4* PAL

    Abstract: 16RP4A 111J 16A4 16X4 16RA8
    Text: 20-Pin PAL/HAIL Devices 16P8A 16RP6A 16RP4A 16RA8 P L ^ _ > ° J 20] VCC T io |T HA CELL — 11^ RA CELL — a lt RA CELL I3 ^ RA CELL » Jo o i]]o 2 — j j ] 03 Tb] o 4 14^ RA CELL — IsQT RA CELL - ] 3 ° 5 I6 ^ [ RA CELL - u 06 17 ^ RA CELL


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    20-Pin 16P8A 16RP8A 16RP6A 16RP4A 16RA8 16R4/B/B-2/B-4 16A4* PAL 16RP4A 111J 16A4 16X4 16RA8 PDF

    Untitled

    Abstract: No abstract text available
    Text: TICPAL18V8-30M, TICPAL18V8 25C ADVANCED EPICm CMOS GENERIC M i D 3 0 8 7 . DECEMBER 1 9 8 7 • 20-Pin Advanced C M OS Generic PAL •


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    TICPAL18V8-30M, TICPAL18V8 20-Pin 25-ns PDF

    Untitled

    Abstract: No abstract text available
    Text: Commercial INC. PEEL 16V8 -5/-7/-10/-15/-25 CMOS Programmable Electrically Erasable Logic Features • Compatible with Popular 16V8 Devices — 16V8 socket and function compatible — Programs with standard 16V8 JEDEC file — 20-pin DIP, SOIC, and PLCC packages


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    20-pin plastiPEEL16V8JQ-15 PEEL16V8SL-15 PEEL16V8SQ-15 PEEL16V8PL-25 PEEL16V8PQ-25 PEEL16V8JL-25 PEEL16V8JQ-25 PEEL16V8SL-25 PEEL16V8SQ-25 PDF

    GAL16VB

    Abstract: National SEMICONDUCTOR GAL16V8 GAL16V8 application notes GAL16v8 algorithm
    Text: GAL16V8 National Semiconductor GAL16V8 Generic Array Logic General Description Features The NSC E2CMOS GAL device combines a high per­ formance CMOS process with electrically erasable floating gate technology. This programmable memory technology applied to array logic provides designers with reconfigurable


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    GAL16V8 GAL16V8 ns-35 emula/9344-36 TL/L/9344-19 GAL16VB National SEMICONDUCTOR GAL16V8 GAL16V8 application notes GAL16v8 algorithm PDF

    Untitled

    Abstract: No abstract text available
    Text: AT18V8Z Features • 20-pin Universal EPLD • Virtually Zero Standby Power • Functional Replacement for Common 20-Pin Programmable Devices Io l = 24 mA • High Performance CMOS EPROM Cell Technology Erasable Reconfigurable 100% Testable • 25 ns and 35 ns Max Propagation Delay Commercial


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    AT18V8Z 20-pin 300-mil-wlde AT18V8Z-25DC AT18V8Z-25JC AT18V8Z-25PC 20DW3 AT18V8Z-30DI AT18V8Z-30JI PDF

    hy18cv8s

    Abstract: low cost eeprom programmer circuit diagram altera EP300 Altera ep310 EP300 HYUNDAI i10 10L8 16H8 HY18CV8 R1-48-*-F
    Text: AL HY18CV8 HYUNDAI SEMICONDUCTOR CMOS EEPLD DESCRIPTION FEATURES T he H Y 18CV8 is a CM O S E lectrically E ra sa­ ble P rogram m able Logic Device E E P L D th at provides a high perform ance; low power, re­ program m able and architecturally flexible alter­


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    HY18CV8 Y18CV8 HY18CV8 20pin hy18cv8s low cost eeprom programmer circuit diagram altera EP300 Altera ep310 EP300 HYUNDAI i10 10L8 16H8 R1-48-*-F PDF

    Untitled

    Abstract: No abstract text available
    Text: H iL a ttic e g a l ig l v s d i ! : : : : Semiconductor •■■■■■ Corporation Hi9h Performance E2CMOS PLD Generic Array Logic FEATURES • HIGH PERFORMANCE E’ CMOS TECHNOLOGY — 3.5 ns Maxim um Propagation Delay — Fmax = 250 MHz — 2.5 ns Maxim um from Clock Input to Data Output


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    GAL16LV8D Q0D4050 PDF

    16LB

    Abstract: No abstract text available
    Text: Devices 20-Pin 16H2/-2 16C1/-2 16L2/-2 16L8/B/B-2/B-4 A/A-2/A-4 bjl=jl£jl£jl=jl£jl=jyi=iy 14H4/-2 12H6/-2 10H8/-2 E E E - AND LOGIC ARRAY E =£> = 0 Ed e = t> =T> i > ID E H > ID E =0 - - AND LOGIC - ARRAY - - n > ID E E 10L8/-2 E E E E - AND - I H > ID


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    20-Pin 10H8/-2 12H6/-2 14H4/-2 16H2/-2 16C1/-2 16L8/B/B-2/B-4 10L8/-2 12L6/-2 14L4/-2 16LB PDF