HEP61
Abstract: hp61 KEP61 MC100 MC100EP16T MC10EP16T
Text: MC10EP16T, MC100EP16T 3.3V / 5VĄECL Differential Receiver/Driver with Internal Termination The EP16T is a world–class differential receiver/driver. The device is functionally equivalent to the EP16 with internal termination resistors. A 50 W resistor is connected from the D input to the VT pin
|
Original
|
PDF
|
MC10EP16T,
MC100EP16T
EP16T
r14525
MC10EP16T/D
HEP61
hp61
KEP61
MC100
MC100EP16T
MC10EP16T
|
MC100
Abstract: MC100EP16T MC10EP16T VT TERMINATION KIT
Text: MC10EP16T, MC100EP16T 3.3V / 5VĄECL Differential Receiver/Driver with Internal Termination The EP16T is a world–class differential receiver/driver. The device is functionally equivalent to the EP16 with internal termination resistors. A 50 W resistor is connected from the D input to the VT pin
|
Original
|
PDF
|
MC10EP16T,
MC100EP16T
EP16T
r14525
MC10EP16T/D
MC100
MC100EP16T
MC10EP16T
VT TERMINATION KIT
|
Untitled
Abstract: No abstract text available
Text: MC10EP16T, MC100EP16T 3.3V / 5V ECL Differential Receiver/Driver with Internal Termination Description The EP16T is a world−class differential receiver/driver. The device is functionally equivalent to the EP16 with internal termination resistors. A 50 W resistor is connected from the D input to the VT pin
|
Original
|
PDF
|
MC10EP16T,
MC100EP16T
EP16T
HEP61
MC10EP16T/D
|
MC100EP16T
Abstract: MC10EP16T
Text: MC10EP16T, MC100EP16T 3.3V / 5V ECL Differential Receiver/Driver with Internal Termination Description The EP16T is a world−class differential receiver/driver. The device is functionally equivalent to the EP16 with internal termination resistors. A 50 W resistor is connected from the D input to the VT pin
|
Original
|
PDF
|
MC10EP16T,
MC100EP16T
EP16T
HEP61ws
MC10EP16T/D
MC100EP16T
MC10EP16T
|
MC100EP16T
Abstract: MC10EP16T
Text: MC10EP16T, MC100EP16T 3.3V / 5V ECL Differential Receiver/Driver with Internal Termination Description The EP16T is a world−class differential receiver/driver. The device is functionally equivalent to the EP16 with internal termination resistors. A 50 W resistor is connected from the D input to the VT pin
|
Original
|
PDF
|
MC10EP16T,
MC100EP16T
EP16T
HEP61
MC10EP16T/D
MC100EP16T
MC10EP16T
|
MC100EP16T
Abstract: MC10EP16T hp61
Text: MC10EP16T, MC100EP16T 3.3V / 5V ECL Differential Receiver/Driver with Internal Termination Description The EP16T is a world−class differential receiver/driver. The device is functionally equivalent to the EP16 with internal termination resistors. A 50 W resistor is connected from the D input to the VT pin
|
Original
|
PDF
|
MC10EP16T,
MC100EP16T
EP16T
HEP61
MC10EP16T/D
MC100EP16T
MC10EP16T
hp61
|
SY100EP11U
Abstract: SY10EP11U
Text: 2.5V/3.3V/5V 1:2 DIFFERENTIAL PECL/LVPECL/ECL FANOUT BUFFER SY10EP11U SY100EP11U FINAL FEATURES • 2.5V, 3.3V and 5V power supply options ■ Guaranteed AC parameters over temperature: • fMAX > 3.0GHz • < 20ps output-to-output skew • < 200ps tr / tf
|
Original
|
PDF
|
SY10EP11U
SY100EP11U
200ps
300ps
SY10/100EP11U
EL11V,
EP11U
SY100EP11U
SY10EP11U
|
SY100EP11UKG
Abstract: HEP11U SY100EP11UKGTR SY100EP11UZGTR SY100EP11UZG xp11 SY10EP11UZG SY100EP11U SY10EP11U XEP11U
Text: 2.5V/3.3V/5V 1:2 DIFFERENTIAL PECL/LVPECL/ECL FANOUT BUFFER Micrel, Inc. ECL Pro SY10EP11U ECL Pro™ SY100EP11U SY10EP11U SY100EP11U FEATURES • 2.5V, 3.3V and 5V power supply options ■ Guaranteed AC parameters over temperature: • fMAX > 3.0GHz • < 20ps output-to-output skew
|
Original
|
PDF
|
SY10EP11U
SY100EP11U
200ps
300ps
SY10/100EP11U
EL11V,
EP11U
M9999-111605
SY100EP11UKG
HEP11U
SY100EP11UKGTR
SY100EP11UZGTR
SY100EP11UZG
xp11
SY10EP11UZG
SY100EP11U
SY10EP11U
XEP11U
|
xep11u
Abstract: No abstract text available
Text: 2.5V/3.3V/5V 1:2 DIFFERENTIAL PECL/LVPECL/ECL FANOUT BUFFER Micrel, Inc. ECL Pro SY10EP11U ECL Pro™ SY100EP11U SY10EP11U SY100EP11U FEATURES • 2.5V, 3.3V and 5V power supply options ■ Guaranteed AC parameters over temperature: • fMAX > 3.0GHz • < 20ps output-to-output skew
|
Original
|
PDF
|
SY10EP11U
SY100EP11U
200ps
300ps
SY10/100EP11U
EL11V,
EP11U
M9999-111605
xep11u
|
Untitled
Abstract: No abstract text available
Text: ECL Pro SY10EP11U SY100EP11U FINAL 2.5V/3.3V/5V 1:2 DIFFERENTIAL PECL/LVPECL/ECL FANOUT BUFFER FEATURES • 2.5V, 3.3V and 5V power supply options ■ Guaranteed AC parameters over temperature: • fMAX > 3.0GHz • < 20ps output-to-output skew • < 200ps tr / tf
|
Original
|
PDF
|
200ps
300ps
SY10EP11U
SY100EP11U
SY10/100EP11U
EL11V,
EP11U
SY100EP11U
|
SY100EP11U
Abstract: SY10EP11U
Text: 2.5V/3.3V/5V 1:2 DIFFERENTIAL PECL/LVPECL/ECL FANOUT BUFFER FEATURES DESCRIPTION • 2.5V, 3.3V and 5V power supply options ■ Guaranteed AC parameters over temperature: • fMAX > 3.0GHz • < 20ps output-to-output skew • < 200ps tr / tf • < 300ps propagation delay
|
Original
|
PDF
|
SY10EP11U
SY100EP11U
200ps
300ps
SY10/100EP11U
EL11V,
EP11U
SY100EP11U
SY10EP11U
|
Untitled
Abstract: No abstract text available
Text: ECL Pro SY10EP11U SY100EP11U FINAL 2.5V/3.3V/5V 1:2 DIFFERENTIAL PECL/LVPECL/ECL FANOUT BUFFER FEATURES • 2.5V, 3.3V and 5V power supply options ■ Guaranteed AC parameters over temperature: • fMAX > 3.0GHz • < 20ps output-to-output skew • < 200ps tr / tf
|
Original
|
PDF
|
SY10EP11U
SY100EP11U
200ps
300ps
SY10/100EP11U
EL11V,
EP11U
|
RSN 3305
Abstract: transmission lines Twisted Pair spice model MMBD701 100EP MBD301 IC CD 4030 pin configuration reflection cofficient free circuit diagram of motherboard 945 ac 625 r 381 substitution AND8020
Text: AND8020/D Termination of ECL Logic Devices Prepared by: Paul Shockman ON Semiconductor Logic Applications Engineering http://onsemi.com APPLICATION NOTE CONTENTS OF APPLICATION NOTE Introduction – DC Termination Analysis Section 3. Thevenin Equivalent/Parallel
|
Original
|
PDF
|
AND8020/D
r14525
RSN 3305
transmission lines Twisted Pair spice model
MMBD701
100EP
MBD301
IC CD 4030 pin configuration
reflection cofficient
free circuit diagram of motherboard 945
ac 625 r 381 substitution
AND8020
|
rsn 3305
Abstract: transmission lines Twisted Pair spice model MC10EP16 100EP 0.001 MF CAPACITOR AND8020
Text: AND8020/D Termination of ECL Logic Devices Prepared by: Paul Shockman ON Semiconductor Logic Applications Engineering http://onsemi.com APPLICATION NOTE CONTENTS OF APPLICATION NOTE Introduction – DC Termination Analysis Section 3. Thevenin Equivalent/Parallel Termination
|
Original
|
PDF
|
AND8020/D
r14525
rsn 3305
transmission lines Twisted Pair spice model
MC10EP16
100EP
0.001 MF CAPACITOR
AND8020
|
|
Untitled
Abstract: No abstract text available
Text: NB6L239 2.5V / 3.3V Any Differential Clock IN to Differential LVPECL OUT ÷1/2/4/8, ÷2/4/8/16 Clock Divider http://onsemi.com Description The NB6L239 is a high−speed, low skew clock divider with two divider circuits, each having selectable clock divide ratios; B1/2/4/8
|
Original
|
PDF
|
NB6L239
B2/4/8/16.
QFN-16
NB6L239/D
|
Untitled
Abstract: No abstract text available
Text: NB6L239 2.5V / 3.3V Any Differential Clock IN to Differential LVPECL OUT ÷1/2/4/8, ÷2/4/8/16 Clock Divider The NB6L239 is a high−speed, low skew clock divider with two divider circuits, each having selectable clock divide ratios; B1/2/4/8 and B2/4/8/16. Both divider circuits drive a pair of differential
|
Original
|
PDF
|
NB6L239
B2/4/8/16.
NB6L239/D
|
Untitled
Abstract: No abstract text available
Text: NB6L239 2.5V / 3.3V Any Differential Clock IN to Differential LVPECL OUT ÷1/2/4/8, ÷2/4/8/16 Clock Divider http://onsemi.com Description The NB6L239 is a high−speed, low skew clock divider with two divider circuits, each having selectable clock divide ratios; B1/2/4/8
|
Original
|
PDF
|
NB6L239
NB6L239
B2/4/8/16.
NB6L239/D
|
Untitled
Abstract: No abstract text available
Text: NB6L239 2.5V / 3.3V Any Differential Clock IN to Differential LVPECL OUT ÷1/2/4/8, ÷2/4/8/16 Clock Divider http://onsemi.com Description The NB6L239 is a high−speed, low skew clock divider with two divider circuits, each having selectable clock divide ratios; B1/2/4/8
|
Original
|
PDF
|
NB6L239
B2/4/8/16.
NB6L239/D
|
2013 qfn-16
Abstract: No abstract text available
Text: NB6L239 2.5V / 3.3V Any Differential Clock IN to Differential LVPECL OUT ÷1/2/4/8, ÷2/4/8/16 Clock Divider http://onsemi.com Description The NB6L239 is a high−speed, low skew clock divider with two divider circuits, each having selectable clock divide ratios; B1/2/4/8
|
Original
|
PDF
|
NB6L239
B2/4/8/16.
QFN-16
NB6L239/D
2013 qfn-16
|
405C
Abstract: 485G NB6L239
Text: NB6L239 2.5V / 3.3V Any Differential Clock IN to Differential LVPECL OUT ÷1/2/4/8, ÷2/4/8/16 Clock Divider http://onsemi.com Description The NB6L239 is a high−speed, low skew clock divider with two divider circuits, each having selectable clock divide ratios; B1/2/4/8
|
Original
|
PDF
|
NB6L239
NB6L239
B2/4/8/16.
NB6L239/D
405C
485G
|
RSN 3305
Abstract: E416
Text: AND8020/D Termination of ECL Logic Devices Prepared by: Paul Shockman ON Semiconductor Logic Applications Engineering http://onsemi.com APPLICATION NOTE CONTENTS OF APPLICATION NOTE Introduction – DC Termination Analysis Section 3. Thevenin Equivalent/Parallel Termination
|
Original
|
PDF
|
AND8020/D
r14525
AND8020/D
RSN 3305
E416
|
motorola HEP cross reference
Abstract: EPT 4045 KPT23 motorola HEP 320 cross reference vef 202 manual KEP52 MC10EP016 HEP 801 hep51 HEP64
Text: BR1513/D Rev. 2, Apr-2001 ECLinPS Plus Device Data ECLinPS Plus Device Data Advanced ECL in Picoseconds BR1513/D Rev. 2, Apr–2001 SCILLC, 2001 Previous Edition 2000 “All Rights Reserved” ECLinPS, ECLinPS Lite, and ECLinPS Plus are trademarks of Semiconductor Components Industries, LLC.
|
Original
|
PDF
|
BR1513/D
Apr-2001
r14525
DLD601
motorola HEP cross reference
EPT 4045
KPT23
motorola HEP 320 cross reference
vef 202 manual
KEP52
MC10EP016
HEP 801
hep51
HEP64
|
full subtractor circuit using decoder
Abstract: full subtractor circuit using nor gates tdb 158 dp VHDL program 4-bit adder 8 bit carry select adder verilog codes full subtractor circuit using nand gate full adder circuit using nor gates full subtractor circuit using nand gates full subtractor circuit nand gates 0-99 counter by using 4 dual jk flip flop
Text: CLA70000 Series High Density CMOS Gate Arrays DS2462 Recent advances in CMOS processing technology and improvements in design architecture have led to the development of a new generation of array-based ASIC products with vastly improved gate integration densities. This
|
Original
|
PDF
|
CLA70000
DS2462
full subtractor circuit using decoder
full subtractor circuit using nor gates
tdb 158 dp
VHDL program 4-bit adder
8 bit carry select adder verilog codes
full subtractor circuit using nand gate
full adder circuit using nor gates
full subtractor circuit using nand gates
full subtractor circuit nand gates
0-99 counter by using 4 dual jk flip flop
|
8 bit carry select adder verilog codes
Abstract: full subtractor circuit using decoder 3 bit carry select adder verilog codes tdb 158 dp gec plessey semiconductor full subtractor circuit using nor gates full adder circuit using nor gates mc2870 VHDL program 4-bit adder 8 bit subtractor
Text: THIS DOCUMENT IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS MARCH 1992 2462 - 3.1 CLA70000 SERIES HIGH DENSITY CMOS GATE ARRAYS Supersedes January 1992 edition - version 2.1 Recent advances in CMOS processing technology and improvements in design architecture have led to the
|
Original
|
PDF
|
CLA70000
8 bit carry select adder verilog codes
full subtractor circuit using decoder
3 bit carry select adder verilog codes
tdb 158 dp
gec plessey semiconductor
full subtractor circuit using nor gates
full adder circuit using nor gates
mc2870
VHDL program 4-bit adder
8 bit subtractor
|