pc133 sdram
Abstract: HYM4V33100DTYG-75
Text: 1Mx32 bits PC133 SDRAM AIMM based on 1Mx16 SDRAM with LVTTL, 2 banks & 4K Refresh HYM4V33100DTYG Series DESCRIPTION The Hynix HYM4V33100DTYG Series are 1Mx16bits Synchronous DRAM Modules. The modules are composed of two 1Mx16bits CMOS Synchronous DRAMs in 400mil 50pin TSOP-II package, on a 132pin glass-epoxy printed circuit board. Two 0.22uF and one
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1Mx32
PC133
1Mx16
HYM4V33100DTYG
1Mx16bits
1Mx16bits
400mil
50pin
132pin
pc133 sdram
HYM4V33100DTYG-75
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Untitled
Abstract: No abstract text available
Text: 132PIN CERAMIC PGA A B Bottom View C 14 13 12 11 10 9 8 7 6 5 4 3 2 1 D P NM L K J HG F E D C B A Index mark Orientation pin J I K L φM F E M H G NOTE Each lead centerline is located within φ 0.50 mm (φ 0.020 inch) of its true position (T.P.) at maximum material condition.
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132PIN
X132RF-100A1-1
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Untitled
Abstract: No abstract text available
Text: 132PIN CERAMIC PGA HEAT SINK TYPE A B (Bottom View) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 C D P N M L K J H G F E D C B A Index mark Orientation pin J I K F E L H G ITEM MILLIMETERS INCHES A 35.56±0.4 1.400±0.016 B 33.56 1.321 C 1.321 D 33.56 35.56±0.4 1.400±0.016
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132PIN
X132RF-100A5-1
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Untitled
Abstract: No abstract text available
Text: 132PIN CERAMIC PGA Bottom View A 14 13 12 11 10 9 8 7 6 5 4 3 2 1 D P N M L K J H G F E D C B A Index mark Orientation pin J I K L φM F E M H G NOTE Each lead centerline is located within φ 0.50 mm (φ 0.020 inch) of its true position (T.P.) at maximum material condition.
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132PIN
X132R-100A1-1
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Untitled
Abstract: No abstract text available
Text: 132PIN CERAMIC PGA A B Bottom View 14 13 12 11 10 9 8 7 6 5 4 3 2 1 C D P NM L K J HG F EDCBA Index mark J Orientation pin I K L F φ M E M H G NOTE Each lead centerline is located within φ 0.50 mm (φ 0.020 inch) of its true position (T.P.) at maximum material condition.
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132PIN
X132RF-100RAMIC
X132RF-100A3-1
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Untitled
Abstract: No abstract text available
Text: 1Mx32 bits PC133 SDRAM AIMM based on 1Mx16 SDRAM with LVTTL, 2 banks & 4K Refresh HYM4V33100DTYG Series DESCRIPTION The Hyundai HYM4V33100DTYG Series are 1Mx16bits Synchronous DRAM Modules. The modules are composed of two 1Mx16bits CMOS Synchronous DRAMs in 400mil 50pin TSOP-II package, on a 132pin glass-epoxy printed circuit board. Two 0.22uF and one
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1Mx32
PC133
1Mx16
HYM4V33100DTYG
1Mx16bits
400mil
50pin
132pin
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Untitled
Abstract: No abstract text available
Text: 132PIN CERAMIC PGA HEAT SINK TYPE A B (Bottom View) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 C D P N M L K J H G F E D C B A Index mark Orientation pin J I K L F E H G ITEM MILLIMETERS INCHES A 35.56±0.4 1.400±0.016 B 33.56 1.321 C 1.321 D 33.56 35.56±0.4 1.400±0.016
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132PIN
X132RF-100A7-1
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Untitled
Abstract: No abstract text available
Text: 132PIN PLASTIC PGA HEAT SINK TYPE A B 14 13 12 11 10 9 8 7 6 5 4 3 2 1 D C (Bottom View) P N M L K J H G F E D C B A Index mark I H G J Orientation pin E K L φM M F X132SF-100A-1 NOTE Each lead centerline is located within φ 0.5 mm (φ 0.020 inch) of its true position (T.P.) at
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132PIN
X132SF-100A-1
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SGRAM
Abstract: 17-18 g
Text: SGRAM Module Code Information MXXXXXXXXXXX - XXXXX 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1. Memory Module M 12. PCB Revision & Type 0 : None 2. Module Configuration 8 : 4 Byte AIMM (132pin) 13. "─" 3~4. Data bits 32 : x32 AIMM w/o SPD 14. Power C : Normal, Self Ref.
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132pin)
SGRAM
17-18 g
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Untitled
Abstract: No abstract text available
Text: 132PIN CERAMIC PGA A Bottom View B C 14 13 12 11 10 9 8 7 6 5 4 3 2 1 D P NM L K J HG F E D C B A Index mark Orientation pin J I K L φM F E M H G NOTE Each lead centerline is located within φ 0.50 mm (φ 0.020 inch) of its true position (T.P.) at maximum material condition.
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132PIN
X132RF-100A4-1
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Untitled
Abstract: No abstract text available
Text: 132PIN CERAMIC PGA Bottom View A 14 13 12 11 10 9 8 7 6 5 4 3 2 1 D P N M L K J H G F E D C B A Orientation pin Index mark J I K F E L H G ITEM A MILLIMETERS INCHES 1.400±0.016 D 35.56±0.4 35.56±0.4 1.400±0.016 E 1.27 0.050 F 2.54 (T.P.) 0.100 (T.P.)
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132PIN
X132RH-100A1-1
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Untitled
Abstract: No abstract text available
Text: 132PIN CERAMIC PGA HEAT SINK TYPE A (Bottom View) B 14 13 12 11 10 9 8 7 6 5 4 3 2 1 C D P N M L K J H G F E D C B A Orientation pin Index mark J I K L F E H G ITEM MILLIMETERS INCHES A 35.56±0.4 1.400±0.016 B 33.56 1.321 C 1.321 D 33.56 35.56±0.4 1.400±0.016
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132PIN
X132RF-100A6-1
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Untitled
Abstract: No abstract text available
Text: 1Mx32 bits PC133 SDRAM AIMM based on 1Mx32 SDRAM with LVTTL, 2 banks & 4K Refresh HYM4V33100BTWG Series DESCRIPTION The Hynix HYM4V33100BTWG Series are 1Mx32bits Synchronous DRAM Modules. The modules are composed of one 1Mx32bits CMOS Synchronous DRAMs in 400mil 86pin TSOP-II package, on a 132pin glass-epoxy printed circuit board. Two 0.22uF and one
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1Mx32
PC133
HYM4V33100BTWG
HYM4V33100BTWG
1Mx32bits
1Mx32bits
400mil
86pin
132pin
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Untitled
Abstract: No abstract text available
Text: 132PIN CERAMIC PGA A Bottom View 14 13 12 11 10 9 8 7 6 5 4 3 2 1 D P N M L K J H G F E D C B A Index mark Orientation pin J I K L F φM E M H G NOTE Each lead centerline is located within φ 0.50 mm (φ 0.020 inch) of its true position (T.P.) at maximum material condition.
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132PIN
X132RH-100A-1
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TMS320LC546A
Abstract: No abstract text available
Text: HEADER LINE 1 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999 D Advanced Multibus Architecture With Three D D D D D D D D D D D D D D D D D D Separate 16-Bit Data Memory Buses and One Program Memory Bus 40-Bit Arithmetic Logic Unit ALU
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SPRS039C
16-Bit
40-Bit
17-Bit
TMS320LC546A
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Untitled
Abstract: No abstract text available
Text: SN54ACT3641 1024 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY SGBS309A – AUGUST 1995 – REVISED APRIL 1998 D D D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Clocked FIFO Buffering Data From Port A to Port B Memory Size: 1024 × 36
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SN54ACT3641
SGBS309A
5962-9560801QYA
5962-9560801NXD
SCAA013A
SCAA008A
SCLA008
SZZU001B,
SDYU001N,
SCET004,
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c6000 flash
Abstract: TMDX320006211
Text: TMS320C6211 FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR TMS320C6711 FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR SPRS073C – AUGUST 1998 – REVISED JUNE 2000 D D D Processors DSPs Fixed-Point: TMS320C6211 Floating-Point: TMS320C6711 – 10-, 6.7-ns Instruction Cycle Time
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TMS320C6211
TMS320C6711
SPRS073C
TMS320C6711
150-MHz
32-Bit
C6211)
C6711)
C6211
c6000 flash
TMDX320006211
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67 1101
Abstract: No abstract text available
Text: TMS320F240 DSP CONTROLLER SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002 D High-Performance Static CMOS Technology D Includes the T320C2xLP Core CPU D D D – Object Compatible With the TMS320C2xx – Source Code Compatible With TMS320C25 – Upwardly Compatible With TMS320C5x
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TMS320F240
SPRS042E
T320C2xLP
TMS320C2xx
TMS320C25
TMS320C5x
132-Pin
50-ns
16-Bit
67 1101
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TMX320VC33
Abstract: SPRS087E tms320vc33pgea120 TMS320C31 TMS320VC33 TMS320VC33-120 TMS320VC33-150 vc33 jtag tms320 lot trace DUPONT CONNECTOR
Text: TMS320VC33 DIGITAL SIGNAL PROCESSOR SPRS087E - FEBRUARY 1999 - REVISED JANUARY 2004 D High-Performance Floating-Point Digital D D D D D D D D D D Signal Processor DSP : - TMS320VC33-150 - 13-ns Instruction Cycle Time - 150 Million Floating-Point Operations
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TMS320VC33
SPRS087E
TMS320VC33-150
13-ns
TMS320VC33-120
17-ns
32-Bit
32-Bit
16-/32-Bit
32-/40-Bit
TMX320VC33
tms320vc33pgea120
TMS320C31
TMS320VC33
TMS320VC33-120
TMS320VC33-150
vc33 jtag
tms320 lot trace
DUPONT CONNECTOR
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Untitled
Abstract: No abstract text available
Text: HYM41V331OODTYG 1Mx32, 1Mx16 based, PC133 DESCRIPTION T he H ynix H Y M 4V33100D TY G Series are 1M x16bits Synchronous DRAM M odules. T he m odules are com posed o f tw o 1M x16bits CM O S S ynchronous DR AM s in 400m il 50pin TSOP-H package, on a 132pin glass-epoxy printed circuit board. T w o 0.22uF and one
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HYM41V331OODTYG
1Mx32,
1Mx16
PC133
4V33100D
x16bits
50pin
132pin
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Untitled
Abstract: No abstract text available
Text: REV DATE DESCRIPTION A 02.03.05 NEW RELEASE B 04.02.04 A MODIFICATION 6 15 5 SERIES HIGH DENSITY CARD EDGE CONN. PITCH : 1 .0 m m 132PIN UNIVERSAL A.G.P ECN NO. AK0402006 NAME N elson ANLG MATERIAL HOUSING : THERMOPLASTIC (U L 94V -0 HOUSING COLOR : BROWN
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132PIN
AK0402006
A6155-*
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Untitled
Abstract: No abstract text available
Text: Dimensions 132Pin 95.0 C L5 2 4 -0 0 0 2 -7 CR24-1 32D- 1.27DS Recommended PCB Dimensions 6-M A X R0.76 Backboard Dimensions 1 2 .7 " -' 3 .8 1 ±0-' 55.88±01 3 . 81±01 11.43±,u V. 274 » OIF • 4 4 ^ 3 2 3 7 0 0 0 3 2 0 3 43*1 Material & Finish Insulator:
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132Pin
CR24-1
1000mS2
41H3237
00D3E01
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SPW 12w
Abstract: TMS380c16 RRU 32
Text: TMS380C26 NETWORK COMMPROCESSOR SPW S010A -APRIL 1992- R E V IS E D MARCH 1993 I • IEEE 802.5 and IBM Token-Ring Network Compatible • Low-Cost Host-Slave I/O Interface Option • IEEE 802.3 and Blue Book Ethernet™ Network Compatible • Selectable Host System-Bus Options
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TMS380C26
S010A
TMS380C16
18K-Byte
16-Mbps
TMS38054
10-Mbps
68xxx
SPW 12w
TMS380c16
RRU 32
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Untitled
Abstract: No abstract text available
Text: SN54ACT3641 1024 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY SGBS309A - AUGUST 1995 - REVISED APRIL 1998 • Free-Running CLKA and CLKB Can Be Asynchronous or Coincident • Output-Ready and Almost-Empty Flags Synchronized by CLKB • Clocked FIFO Buffering Data From Port A
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SN54ACT3641
SGBS309A
5962-9560801QYA
5962-9560801NXD
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