100-PIN CPGA PACKAGE PIN-OUT DIAGRAM Search Results

100-PIN CPGA PACKAGE PIN-OUT DIAGRAM Result Highlights (5)

Part	Manufacturer	Description
TPH9R00CQH	Toshiba Electronic Devices & Storage Corporation	MOSFET, N-ch, 150 V, 64 A, 0.009 Ohm@10V, SOP Advance / SOP Advance(N)
TPH2R408QM	Toshiba Electronic Devices & Storage Corporation	MOSFET, N-ch, 80 V, 120 A, 0.00243 Ohm@10V, SOP Advance
XPH2R106NC	Toshiba Electronic Devices & Storage Corporation	N-ch MOSFET, 60 V, 110 A, 0.0021 Ω@10V, SOP Advance(WF)
XPH3R206NC	Toshiba Electronic Devices & Storage Corporation	N-ch MOSFET, 60 V, 70 A, 0.0032 Ω@10V, SOP Advance(WF)
TPH4R008QM	Toshiba Electronic Devices & Storage Corporation	MOSFET, N-ch, 80 V, 86 A, 0.004 Ohm@10V, SOP Advance(N)

100-PIN CPGA PACKAGE PIN-OUT DIAGRAM Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
mobile MOTHERBOARD CIRCUIT diagram Abstract: POWER COMMAND HM 1300 motherboard Northbridge gigabyte MOTHERBOARD CIRCUIT diagram amd am2 socket pin diagram AG13 AJ21 AN17 C001 amd duron PIN LAYOUT voltage ground Text: Preliminary Information Mobile AMD Athlon 4 TM Processor Model 6 CPGA Data Sheet Featuring: Publication # 24319 Rev: E Issue Date: November 2001 Preliminary Information 2000, 2001 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced	Original		PDF
grp 328 Abstract: No abstract text available Text: ispLSI 1048C/883 In-System Programmable High Density PLD Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 8000 PLD Gates — 96 I/O Pins, 12 Dedicated Inputs, 2 Global Output Enables — 288 Registers — High-Speed Global Interconnect — Wide Input Gating for Fast Counters, State	Original	1048C/883 I/O15 I/O12 I/O23 I/O20 I/O17 I/O14 I/O21 I/O18 I/O16 grp 328	PDF
Diode smd f6 Abstract: 5962-9558701MXC Text: ispLSI 1048C/883 In-System Programmable High Density PLD Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 8000 PLD Gates — 96 I/O Pins, 12 Dedicated Inputs, 2 Global Output Enables — 288 Registers — High-Speed Global Interconnect — Wide Input Gating for Fast Counters, State	Original	1048C/883 I/O15 I/O12 I/O23 I/O20 I/O17 I/O14 I/O21 I/O18 I/O16 Diode smd f6 5962-9558701MXC	PDF
1048C Abstract: No abstract text available Text: ispLSI and pLSI 1048C ® High-Density Programmable Logic Functional Block Diagram Output Routing Pool Output Routing Pool F7 F6 F5 F4 F3 F2 F1 F0 E7 E6 E5 E4 E3 E2 E1 E0 D7 A2 A4 IG N D Q Logic Global Routing Pool GRP A5 A6 A7 D B0 B1 B2 B3 B4 B5 B6 B7	Original	1048C Military/883 1048C-70LQ 128-Pin 1048C-50LQ 1048C	PDF
Untitled Abstract: No abstract text available Text: ispLSI 1048C/883 In-System Programmable High Density PLD Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 8000 PLD Gates — 96 I/O Pins, 12 Dedicated Inputs, 2 Global Output Enables — 288 Registers — High-Speed Global Interconnect — Wide Input Gating for Fast Counters, State	Original	1048C/883 I/O21 I/O18 I/O16 I/O13 I/O11 1048C 0212-80B-isp1048C 1048C-50LG/883	PDF
1048C Abstract: No abstract text available Text: Specifications ispLSI and pLSI 1048C ispLSI and pLSI 1048C ® High-Density Programmable Logic Functional Block Diagram Output Routing Pool Output Routing Pool F7 F6 F5 F4 F3 F2 F1 F0 E7 E6 E5 E4 E3 E2 E1 E0 D7 A2 A4 IG N D Q Logic Global Routing Pool GRP	Original	1048C Military/883 1048C	PDF
AM29516 Abstract: CY7C516 LMU16 Text: HMU16/883 16 x 16-Bit CMOS Parallel Multiplier April 1997 Features Description • This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. The HMU16/883 is a high speed, low power CMOS 16 x 16-bit	Original	HMU16/883 16-Bit MIL-STD883 HMU16/883 16-bit 32-Bit AM29516 CY7C516 LMU16	PDF
CY7C516 Abstract: AM29516 LMU16 10X11 Text: HMU16/883 16 x 16-Bit CMOS Parallel Multiplier October 1997 Features Description • This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. The HMU16/883 is a high speed, low power CMOS 16 x 16-bit	Original	HMU16/883 16-Bit MIL-STD883 HMU16/883 16-bit 32-Bit CY7C516 AM29516 LMU16 10X11	PDF
1048C Abstract: cpga 476 1048C50LQI 1048C-70 Text: Specifications ispLSI and pLSI 1048C ® ispLSI and pLSI 1048C High-Density Programmable Logic Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 8000 PLD Gates — 96 I/O Pins, 12 Dedicated Inputs, 2 Global Output Enables — 288 Registers	Original	1048C Military/883 1048C cpga 476 1048C50LQI 1048C-70	PDF
256-CPGA Abstract: QL4016 QL4090 100CQFP Text: Military QuickRAM 90,000 Usable PLD Gate QuickRAM Combining Performance, Density and Embedded RAM Military QuickRAM DEVICE HIGHLIGHTS FEATURES Device Highlights Features High Performance and High Density Total of 316 I/O pins • Up to 90,000 Usable PLD Gates with 316 I/Os	Original	16-bit 152-bit 256-CPGA QL4016 QL4090 100CQFP	PDF
Diode smd f6 Abstract: 1048C isplsi1048c Text: ispLSI 1048C In-System Programmable High Density PLD Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 8000 PLD Gates — 96 I/O Pins, 12 Dedicated Inputs, 2 Global Output Enables — 288 Registers — High-Speed Global Interconnect — Wide Input Gating for Fast Counters, State	Original	1048C Military/883 0212-80B-isp1048C 1048E spLSI1048C-70LQS 1048C-50LQ 1048C-50LQIS 128-Pin Diode smd f6 1048C isplsi1048c	PDF
32565 Abstract: K15-Y LSC 132 isplsi 3256 Text: Specifications ispLSI and pLSI 3256 ispLSI and pLSI 3256 ® High Density Programmable Logic Functional Block Diagram • HIGH PERFORMANCE E CMOS TECHNOLOGY — fmax = 77 MHz Maximum Operating Frequency — tpd = 15 ns Propagation Delay — TTL Compatible Inputs and Outputs	Original		PDF
tcx 15 Abstract: No abstract text available Text: HMU16/883 TM 16 x 16-Bit CMOS Parallel Multiplier October 1997 itle MU /883 bt x -Bit OS ralltier utho ) eyrds ter- Features Description • This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1.	Original	HMU16/883 16-Bit HMU16/883 32-bit 31-bit tcx 15	PDF
isp1032 Abstract: g10 smd transistor 5962-9308501MXC Text: ispLSI 1032/883 In-System Programmable High Density PLD Features Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — High Speed Global Interconnect — 6000 PLD Gates — 64 I/O Pins, Eight Dedicated Inputs — 192 Registers — Wide Input Gating for Fast Counters, State	Original	I/O12 I/O10 488A-32-isp/883 0212-80B-isp1032 MILITARY/883 1032-60LG/883 5962-9308501MXC 84-Pin 041A-32-ispmil isp1032 g10 smd transistor 5962-9308501MXC	PDF

tagl2 Abstract: S 0680 LR3000 DK3T TAG23 LR3000AKC33 lr3000gc20 MM7200 TAG24 Text: Chapter 12: Specifications This chapter presents the following information for the LR3000 and LR3000A processors: • LR3000 Electrical Specifications • LR3000A Electrical Specifications • Timing Diagrams • Mechanical, Pinout, and Mounting Information	OCR Scan	LR3000 LR3000A 144-pin 172-pin tagl2 S 0680 DK3T TAG23 LR3000AKC33 lr3000gc20 MM7200 TAG24	PDF
Untitled Abstract: No abstract text available Text: Lattice is p L S ra n d pLSF 3256 High Density Programmable Logic Functional Block Diagram Features HIGH DENSITY PROGRAMMABLE LOGIC — High Speed Global Interconnect — 128 I/O Pins — 11000 PLD Gates — 384 Registers — Wide Input Gating for Fast Counters, State	OCR Scan	ijf39 0212Aisp/3256 3256-70LM160 3256-70LG167 3256-50LM160 3256-50LG167 3256-50LG167	PDF
Untitled Abstract: No abstract text available Text: LATTICE SEMICONDUCTOR Lattica bûE D • 5301^4= 0QG27Ü7 b4T HILA T pLSI and ispLSI 3256 High Density Programmable Logic Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — — — — — High Speed Global Interconnect 128 I/O Pins	OCR Scan	0QG27Ã 3256-80LM160 160-Pin 3256-80LG167 167-Pin 3256-70LM160 3256-70LG167 3256-50LM160	PDF
4BB7 Abstract: No abstract text available Text: IliLattice ispLSI’and pLSI 3256 High Density Programmable Logic Features_ J Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 128 I/O Pins — 11000 PLD Gates — 384 Registers — High Speed Global Interconnect	OCR Scan	3256-70LM 160-Pin 3256-70LG 167-Pin 3256-50LM 3256-50LG 4BB7	PDF
ISPLSI3320-70LQ N Abstract: No abstract text available Text: Specifications ispLSI and pLSI 1048C Lattice ispLSI and pLSI 1048C ;Semiconductor I Corporation High-Density Programmable Logic Features Functional Block Diagram HIGH-DENSITY PROGRAMMABLE LOGIC — 8000 PLD Gates — 96 I/O Pins, 12 Dedicated Inputs, 2 Global Output	OCR Scan	1048C Military/883 ispLS11048C-70LQ 128-Pin ispLS11048C-50LQ I1048C-70LQ I1048C-50LQ ISPLSI3320-70LQ N	PDF
Untitled Abstract: No abstract text available Text: Latticc i s p ; ; ; Semiconductor •■■ Corporation L S I 1 4 8 C In-System Programmable High Density PLD Features Functional Block Diagram HIGH-DENSITY PROGRAMMABLE LOGIC — 8000 PLD Gates — 96 I/O Pins, 12 Dedicated Inputs, 2 Global Output Enables	OCR Scan	u------------------------------------70 1048C-70LQ 128-Pin 1048C -50LQ 1048C-50LQI -50LG	PDF
w584 Abstract: V068 Text: Specifications ispLSI and pLSI 3256 Lattice ispLSrand pLSI 3256 I Semiconductor I Corporation High Density Programmable Logic Features Functional Block Diagram H1GH-DENSITY PROGRAMMABLE LOGIC — 128 I/O Pins — 11000 PLD Gates — 384 Registers — High Speed Global Interconnect	OCR Scan	0212Aisp/3256 3256-70LM 160-Pin 3256-70LG 167-Pin 3256-50LM 3256-50LG w584 V068	PDF
ncl 055 Abstract: No abstract text available Text: Lattica ispLSI' and pLSI' 1048C ;Semiconductor ICorporation High-Density Programmable Logic Features Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 8000 PLD Gates — 96 I/O Pins, 12 Dedicated Inputs, 2 Global Output Enables — 288 Registers	OCR Scan	1048C ncl 055	PDF
Untitled Abstract: No abstract text available Text: Programmable Peripheral PSD100 DSP Peripheral with Memory Preliminary Key Features □ Programmable System Device PSD □ Major System Functions — 128K EPROM — 32K SRAM — Programmable Address Decoder □ Low Power Consumption □ Fully Compatible with TMS320LCXX	OCR Scan	PSD100 TMS320LCXX PSD100 PSD100-45J 44-pin PSD100-45L* PSD100-45X PSD100-55J	PDF
pj45 Abstract: smd code pj4 smd code book L2 5962-9558701M 0180-B RK 94 SMD General Semiconductor Text: Lattice ispLSI* and p L S I° 1 0 4 8 C ; Semiconductor I Corporation High-Density Programmable Logic Functional Block Diagram F e a tu re s • HIGH-DENSITY PROGRAMMABLE LOGIC — 8000 PLD Gates — 96 I/O Pins, 12 Dedicated Inputs, 2 Global Output Enables	OCR Scan	Military/883 Non-Volati----70 1048C 1048C-70LQ 1048C-50LQ 1048C-50LQ 128-Pin pj45 smd code pj4 smd code book L2 5962-9558701M 0180-B RK 94 SMD General Semiconductor	PDF

100-PIN CPGA PACKAGE PIN-OUT DIAGRAM Search Results

100-PIN CPGA PACKAGE PIN-OUT DIAGRAM Result Highlights (5)

100-PIN CPGA PACKAGE PIN-OUT DIAGRAM Datasheets Context Search

mobile MOTHERBOARD CIRCUIT diagram

grp 328

Diode smd f6

1048C

Untitled

1048C

AM29516

CY7C516

1048C

256-CPGA

Diode smd f6

32565

tcx 15

isp1032

tagl2

Untitled

Untitled

4BB7

ISPLSI3320-70LQ N

Untitled

w584

ncl 055

Untitled

pj45